//////////////div_10/////////////
module div_10( enable, in, out );
input enable, in;
output out;
reg out;
reg [3:0] cntr;
initial
begin
cntr <= 4'b0000;
end
always @( posedge in )
begin
if( !enable ) cntr <= 4'b0000;
else if( cntr == 4'b1010 ) cntr <= 4'b0000;
else cntr <= cntr + 1;
end
always @ ( posedge in )begin
if( !enable ) out <= 1'b0;
else if( cntr <= 4'b0100 ) out <= 1'b0;
else out <= 1'b1;
end
endmodule
//////////////////////////////////////////
/////////PFD////////////////////////
module pfd( u1, u2, up, dn);
input u1;
input u2;
output up;
output dn;
// output rst;
//wire d = 1;
wire rst;
d_ff D1 ( .d_in(1'b1), .clk(u1), .reset(rst), .d_out(up) );
d_ff D2 ( .d_in(1'b1), .clk(u2), .reset(rst), .d_out(dn) );
and ( rst, up, dn );
endmodule
module d_ff ( d_in, clk, reset, d_out );
input d_in;
input clk;
input reset;
output d_out;
reg d_out;
always @ ( posedge reset or posedge clk )
begin
if (reset)
d_out = 1'b0;
else
d_out = d_in;
end
endmodule
///////////////////////////////////
/////controller///////////////////
module controller ( reset, clk, up, dn, DCO_CONTRL );
input reset, up, dn, clk;
output [7:0] DCO_CONTRL;
reg freq_acq_mode, ph_acq_mode, step;
reg [7:0] DCO_CONTRL;
wire cond1, cond2, cond3, condp1, condp2;
reg [7:0] cntf1, cntf2, cntp1, cntp2;
reg [3:0] spd_cnt;
reg [6:0] ss;
reg [6:0] s_step;
assign cond1 = freq_acq_mode && step,
cond2 = freq_acq_mode && up,
cond3 = freq_acq_mode && dn,
condp1 = ph_acq_mode && up,
condp2 = ph_acq_mode && dn;
always @ (posedge clk )
begin
if (reset ) begin
DCO_CONTRL <= 8'd127;
ss <= 7'd64;
freq_acq_mode <= 1;
ph_acq_mode <= 0;
cntf1 <= 0;
cntf2 <= 0;
step <= 0;
end
else if (freq_acq_mode) begin
if (s_step == 1) step <= 1;
else step <= 0;
case ({cond1, cond2, cond3})
3'b100:begin
DCO_CONTRL <= DCO_CONTRL;
s_step <= ss;
freq_acq_mode <= 0;
ph_acq_mode <= 1;
cntf1 <= 0;
cntf2 <= 0;
end
3'b010:begin
freq_acq_mode <= 1;
ph_acq_mode <= 0;
cntf2 <= 0;
cntf1 <= cntf1 + 1;
DCO_CONTRL <= DCO_CONTRL + 1;
s_step <= s_step;
if (cntf1 <= 1) begin
s_step <= ss;
s_step <= s_step / 2;
ss <= s_step;
end
end
3'b001:begin
freq_acq_mode <= 1;
ph_acq_mode <= 0;
cntf2 <= cntf2 + 1;
DCO_CONTRL <= DCO_CONTRL - 1;
cntf1 <= 0;
s_step <= s_step;
if (cntf2 <= 1) begin
s_step <= ss;
s_step <= s_step / 2;
ss <= s_step;
end
end
default: begin
DCO_CONTRL <= 0;
s_step <= s_step;
cntf1 <= 0;
cntf2 <= 0;
freq_acq_mode <= 1;
ph_acq_mode <= 0;
end
endcase
end
else if (ph_acq_mode) begin
case ( {condp1, condp2} )
2'b10:
begin
cntp2 <= 0;
if (cntp1 > 1) begin
cntp1 <= cntp1 + 1;
spd_cnt <= spd_cnt + 1;
s_step <= s_step;
if (spd_cnt == 8) begin
s_step <= s_step * 2;
spd_cnt <= 0;
cntp1 <= 0;
end
end
else begin
cntp2 <= 0;
s_step <= s_step;
if (s_step != 1) s_step <= s_step / 2;
cntp1 <= cntp1 + 1;
spd_cnt <= spd_cnt + 1;
end
end
2'b01:begin
cntp1 <= 0;
if (cntp2 > 1) begin
cntp2 <= cntp2 + 1;
spd_cnt <= spd_cnt + 1;
s_step <= s_step;
if (spd_cnt == 8) begin
s_step <= s_step * 2;
spd_cnt <= 0;
cntp2 <= 0;
end
end
else begin
cntp1 <= 0;
s_step <= s_step;
if (s_step != 1) s_step <= s_step / 2;
cntp2 <= cntp2 + 1;
spd_cnt <= spd_cnt + 1;
end
end
default : begin
cntp1 <= 0;
cntp2 <= 0;
s_step <= 0;
spd_cnt <= 0;
end
endcase
end
end
endmodule
//////////////////////////////////
/////dig_cntrl_osc/////////////
module dig_cntrl_osc ( enable, DCO_CONTRL, DCO_OUT );
input enable;
input [7:0] DCO_CONTRL;
output DCO_OUT;
wire cell4_out, cell3_out, cell2_out;
//assign cell4in = DCO_OUTB;///
not invsel0( CONTRL6b, DCO_CONTRL[6] );
not invsel1( CONTRL7b, DCO_CONTRL[7] );
and andsel0( sel0, CONTRL7b, CONTRL6b );
and andsel1( sel1, CONTRL7b, DCO_CONTRL[6] );
and andsel2( sel2, DCO_CONTRL[7], CONTRL6b );
and andsel3( sel3, DCO_CONTRL[7], DCO_CONTRL[6] );
nand nandout( DCO_OUTB, cell1_out, enable );
not INV1( DCO_OUT1B, DCO_OUTB );
not INV3( DCO_OUT, DCO_OUTB );
not INV2( DCO_OUT2B, DCO_OUTB );
assign cell4_in = sel0 ? DCO_OUTB : 1'b0;
assign cell3_in = sel1 ? DCO_OUT2B : cell4_out;
assign cell2_in = sel2 ? DCO_OUT : cell3_out;
assign cell1_in = sel3 ? DCO_OUT1B : cell2_out;
DCO_CELL cell1( DCO_CONTRL[5:0], cell1_in, cell1_out );
DCO_CELL cell2( DCO_CONTRL[5:0], cell2_in, cell2_out );
DCO_CELL cell3( DCO_CONTRL[5:0], cell3_in, cell3_out );
DCO_CELL cell4( DCO_CONTRL[5:0], cell4_in, cell4_out );
endmodule
/////////////////////////////////