`timescale 1ns / 1ps
// Module Name: FIR_Filter
module FIR_Filter(clk, reset, my_data_in, my_data_out);
parameter N = 8;
input clk, reset;
input [N-1:0] my_data_in;
output reg [N-1:0] my_data_out;
// coefficients defination
// Moving Average Filter, 3rd order
wire [7:0] b0 = 8'b00001010;
wire [7:0] b1 = 8'b00010000;
wire [7:0] b2 = 8'b00101000;
wire [7:0] b3 = 8'b01000000;
wire [7:0] b4 = 8'b00101000;
wire [7:0] b5 = 8'b00010000;
wire [7:0] b6 = 8'b00001010;
wire [N-1:0] x1, x2, x3, x4, x5, x6;
// Create delays i.e x[n-1], x[n-2], .. x[n-N]
// Instantiate D Flip Flops
DFF DFF0(clk, 1'b0, my_data_in, x1); // x[n-1]
DFF DFF1(clk, 1'b0, x1, x2); // x[x[n-2]]
DFF DFF2(clk, 1'b0, x2, x3); // x[n-3]
DFF DFF3(clk, 1'b0, x3, x4);
DFF DFF4(clk, 1'b0, x4, x5);
DFF DFF5(clk, 1'b0, x5, x6);
// Multitiplication
wire [N-1:0] Multi0, Multi1, Multi2, Multi3, Multi4, Multi5, Multi6;
assign Multi0 = my_data_in * b0;
assign Multi1 = x1 * b1;
assign Multi2 = x2 * b2;
assign Multi3 = x3 * b3;
assign Multi4 = x4 * b4;
assign Multi5 = x5 * b5;
assign Multi6 = x6 * b6;
// Addition operation
wire [N-1:0] Add_final_value;
assign Add_final_value = Multi0 + Multi1 + Multi2 + Multi3 + Multi4 + Multi5 + Multi6;
// Final calculation to output
always@(posedge clk)
my_data_out <= Add_final_value;
endmodule
module DFF(clk, reset, my_data_in, data_delayed);
parameter N = 8;
input clk, reset;
input [N-1:0] my_data_in;
output reg [N-1:0] data_delayed;
always@(posedge clk, posedge reset)
begin
if (reset)
data_delayed <= 0;
else
data_delayed <= my_data_in;
end
endmodule