If you see the datasheet it has a graph between output noise voltage and output voltage. Increasing the output voltage increases the noise voltage.
Also increase in output current levels causes increase in dropout voltage.
The dropout voltage is the difference between the output voltage and the input voltage at which the circuit quits regulation with further reductions in input voltage.
So if you are keeping your input voltage fixed, an increase in output current means more dropout means level of output voltage voltage increases marginally and hence output noise level should increase.
Well please check with seniors here and I really dont know how to calculate the actual numbers. But just make sure you are doing everything at circuit level to minimize the noise
Some more info
An LDO’s internal voltage reference is the primary source for output noise. It is usually specified in microvolts rms over a specific bandwidth, such as 25 μV rms from 1 kHz to 100 kHz. This low level noise is much lower than the switching transients and harmonics from a switch mode dc-to-dc converter. Some LDOs feature a bypass pin to filter
reference voltage noise with a capacitor to ground. Following the data sheet specified input, output, and bypass capacitors usually results in a unproblematic noise level.
https://focus.ti.com/lit/an/slyt201/slyt201.pdf
https://www.analog.com/static/imported-files/pwr_mgmt/PM_ldo_design_08451b.pdf