output netlist probelm

[smaz]

Hi
I wrote a very simple counter in VHDL and then simulated to see whether it works or not. Then I sent it to the design compiler to do synthesize without any constraints. after that I made an output netlist in VHDL and brought it back to simulator it didn't work while it was a simple counter. for detecting the problem,I decrease the design to 2-bit counter and did the same story and interestingly this time it works then I changed it to 4-bit counter and its synthesized output didn't work then I came up with making the output netlist in verilog and now its synthesized output works for any number of bit.
1-Does any body know what is the problem?
2-And does anybody know which is possible to produce the output netlist in Cadence RTL compiler in VHDL format?
Thanks in advance for your help.

 

[rca]

In general, the netlist is always written in Verilog. I write the rtl code in VHDL or Verilog, and always used the VHDL format as output of EDA tool.
Dd you add the timing info? Did you run a gate simulation with timing ...

 

[smaz]

No. no constraints was used during the synthesis. And the output file only includes the instances without any timing info.

- - - Updated - - -

No. no constraints was used during the synthesis. And the output file only includes the instances without any timing info.

 

[tariq786]

put your code and the netlist here so that others can take a look. use code tags to put your code in a neat format.

//your code goes here

 

[rca]

Your netlist contains standard cells. To simulate your netlist, you must have compile the std cell model. This std cell model have some timing info. Then you need to simulate without timing aspect to be sure to simulate as functional.

Did you runs LEC tool between the netlist and your rtl code?

 

[smaz]

Thanks for your help.

Here is my VHDL CODE, I am using N to make the design generic:

library IEEE;
use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity counter is
	generic(N:integer:=4);
	port(clk,en:in std_logic;
	o:out std_logic_vector(N downto 0));
end;

architecture synth of counter is
signal io:std_logic_vector(N downto 0);
begin
	counter_polyphase:process (clk)
	begin
		if (rising_edge(clk)) then
			if(en='0') then
				io<=(others=>'0');
			else
				io<=std_logic_vector(signed(io)+1);
			end if;
		end if;
		
	end process counter_polyphase;
	o<=io; 	
end synth;

For doing the simulating, I am using the Active-Hdl tool and also compiled the std cell library file. I know only VHDL, and none of std cell library files don't include any timing info. I am beginner in working with IC design tools and I don't know about the LEC tool, If you all have more info or docs, please let me know.
Here are the output netlist in VHDL and VERILOG:

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_counter is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_counter;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_counter.all;

entity counter_DW01_inc_0 is

   port( A : in std_logic_vector (4 downto 0);  SUM : out std_logic_vector (4 
         downto 0));

end counter_DW01_inc_0;

architecture SYN_rpl of counter_DW01_inc_0 is

   component HS65_LL_CNIVX3
      port( A : in std_logic;  Z : out std_logic);
   end component;
   
   component HS65_LL_CNXOR2X38
      port( A, S : in std_logic;  Z : out std_logic);
   end component;
   
   component HS65_LL_CNNAND2X18
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component HS65_LL_CNOR3X15
      port( A, B, C : in std_logic;  Z : out std_logic);
   end component;
   
   component HS65_LL_CNNOR2AX15
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   signal SUM_4_port, SUM_3_port, SUM_2_port, SUM_1_port, SUM_0_port, n1, n2, 
      n3, n4, n5, n6 : std_logic;

begin
   SUM <= ( SUM_4_port, SUM_3_port, SUM_2_port, SUM_1_port, SUM_0_port );
   
   U1 : HS65_LL_CNXOR2X38 port map( A => A(4), S => n1, Z => SUM_4_port);
   U2 : HS65_LL_CNNOR2AX15 port map( A => A(3), B => n2, Z => n1);
   U3 : HS65_LL_CNXOR2X38 port map( A => n3, S => n2, Z => SUM_3_port);
   U4 : HS65_LL_CNOR3X15 port map( A => SUM_0_port, B => n4, C => n5, Z => n2);
   U5 : HS65_LL_CNIVX3 port map( A => A(1), Z => n4);
   U6 : HS65_LL_CNIVX3 port map( A => A(3), Z => n3);
   U7 : HS65_LL_CNXOR2X38 port map( A => n6, S => n5, Z => SUM_2_port);
   U8 : HS65_LL_CNIVX3 port map( A => A(2), Z => n5);
   U9 : HS65_LL_CNNAND2X18 port map( A => A(1), B => A(0), Z => n6);
   U10 : HS65_LL_CNXOR2X38 port map( A => A(1), S => A(0), Z => SUM_1_port);
   U11 : HS65_LL_CNIVX3 port map( A => A(0), Z => SUM_0_port);

end SYN_rpl;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_counter.all;

entity counter is

   port( clk, en : in std_logic;  o : out std_logic_vector (4 downto 0));

end counter;

architecture SYN_synth of counter is

   component counter_DW01_inc_0
      port( A : in std_logic_vector (4 downto 0);  SUM : out std_logic_vector 
            (4 downto 0));
   end component;
   
   component HS65_LL_CNAND2X17
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component HS65_LL_CNSDFPRQTX15
      port( D, TI, TE, CP, RN : in std_logic;  TQ, Q : out std_logic);
   end component;
   
   signal o_4_port, o_3_port, o_2_port, o_1_port, o_0_port, N2, N3, N4, N5, N6,
      n1, n2_port, n3_port, n4_port, n5_port, n6_port, n7, n8, n9, n10, n11, 
      n_1000, n_1001, n_1002, n_1003, n_1004 : std_logic;

begin
   o <= ( o_4_port, o_3_port, o_2_port, o_1_port, o_0_port );
   
   io_reg_0_inst : HS65_LL_CNSDFPRQTX15 port map( D => n11, TI => n6_port, TE 
                           => n6_port, CP => clk, RN => n1, TQ => n_1000, Q => 
                           o_0_port);
   io_reg_1_inst : HS65_LL_CNSDFPRQTX15 port map( D => n10, TI => n5_port, TE 
                           => n5_port, CP => clk, RN => n1, TQ => n_1001, Q => 
                           o_1_port);
   io_reg_2_inst : HS65_LL_CNSDFPRQTX15 port map( D => n9, TI => n4_port, TE =>
                           n4_port, CP => clk, RN => n1, TQ => n_1002, Q => 
                           o_2_port);
   io_reg_3_inst : HS65_LL_CNSDFPRQTX15 port map( D => n8, TI => n3_port, TE =>
                           n3_port, CP => clk, RN => n1, TQ => n_1003, Q => 
                           o_3_port);
   io_reg_4_inst : HS65_LL_CNSDFPRQTX15 port map( D => n7, TI => n2_port, TE =>
                           n2_port, CP => clk, RN => n1, TQ => n_1004, Q => 
                           o_4_port);
   U3 : HS65_LL_CNAND2X17 port map( A => en, B => N6, Z => n7);
   U4 : HS65_LL_CNAND2X17 port map( A => N5, B => en, Z => n8);
   U5 : HS65_LL_CNAND2X17 port map( A => N4, B => en, Z => n9);
   U6 : HS65_LL_CNAND2X17 port map( A => N3, B => en, Z => n10);
   U7 : HS65_LL_CNAND2X17 port map( A => N2, B => en, Z => n11);
   n1 <= '1';
   n2_port <= '0';
   n3_port <= '0';
   n4_port <= '0';
   n5_port <= '0';
   n6_port <= '0';
   add_21 : counter_DW01_inc_0 port map( A(4) => o_4_port, A(3) => o_3_port, 
                           A(2) => o_2_port, A(1) => o_1_port, A(0) => o_0_port
                           , SUM(4) => N6, SUM(3) => N5, SUM(2) => N4, SUM(1) 
                           => N3, SUM(0) => N2);

end SYN_synth;

module counter_DW01_inc_0 ( A, SUM );
  input [4:0] A;
  output [4:0] SUM;
  wire   n1, n2, n3, n4, n5, n6;

  HS65_LL_CNXOR2X38 U1 ( .A(A[4]), .S(n1), .Z(SUM[4]) );
  HS65_LL_CNNOR2AX15 U2 ( .A(A[3]), .B(n2), .Z(n1) );
  HS65_LL_CNXOR2X38 U3 ( .A(n3), .S(n2), .Z(SUM[3]) );
  HS65_LL_CNOR3X15 U4 ( .A(SUM[0]), .B(n4), .C(n5), .Z(n2) );
  HS65_LL_CNIVX3 U5 ( .A(A[1]), .Z(n4) );
  HS65_LL_CNIVX3 U6 ( .A(A[3]), .Z(n3) );
  HS65_LL_CNXOR2X38 U7 ( .A(n6), .S(n5), .Z(SUM[2]) );
  HS65_LL_CNIVX3 U8 ( .A(A[2]), .Z(n5) );
  HS65_LL_CNNAND2X18 U9 ( .A(A[1]), .B(A[0]), .Z(n6) );
  HS65_LL_CNXOR2X38 U10 ( .A(A[1]), .S(A[0]), .Z(SUM[1]) );
  HS65_LL_CNIVX3 U11 ( .A(A[0]), .Z(SUM[0]) );
endmodule


module counter ( clk, en, o );
  output [4:0] o;
  input clk, en;
  wire   N2, N3, N4, N5, N6, n7, n8, n9, n10, n11;

  HS65_LL_CNSDFPRQTX15 \io_reg[0]  ( .D(n11), .TI(1'b0), .TE(1'b0), .CP(clk), 
        .RN(1'b1), .Q(o[0]) );
  HS65_LL_CNSDFPRQTX15 \io_reg[1]  ( .D(n10), .TI(1'b0), .TE(1'b0), .CP(clk), 
        .RN(1'b1), .Q(o[1]) );
  HS65_LL_CNSDFPRQTX15 \io_reg[2]  ( .D(n9), .TI(1'b0), .TE(1'b0), .CP(clk), 
        .RN(1'b1), .Q(o[2]) );
  HS65_LL_CNSDFPRQTX15 \io_reg[3]  ( .D(n8), .TI(1'b0), .TE(1'b0), .CP(clk), 
        .RN(1'b1), .Q(o[3]) );
  HS65_LL_CNSDFPRQTX15 \io_reg[4]  ( .D(n7), .TI(1'b0), .TE(1'b0), .CP(clk), 
        .RN(1'b1), .Q(o[4]) );
  HS65_LL_CNAND2X17 U3 ( .A(en), .B(N6), .Z(n7) );
  HS65_LL_CNAND2X17 U4 ( .A(N5), .B(en), .Z(n8) );
  HS65_LL_CNAND2X17 U5 ( .A(N4), .B(en), .Z(n9) );
  HS65_LL_CNAND2X17 U6 ( .A(N3), .B(en), .Z(n10) );
  HS65_LL_CNAND2X17 U7 ( .A(N2), .B(en), .Z(n11) );
  counter_DW01_inc_0 add_21 ( .A(o), .SUM({N6, N5, N4, N3, N2}) );
endmodule

Another strange problem is that the simulation result of output netlist written in Verilog in Active-Hdl and Modelsim are different. In other words, when the counter is enabled, in modelsim, it takes more time to start to count while in Active-Hdl, it starts to count in proper time.
by the way, I didn't understand it is possible to make the output netlist in vhdl in Cadence RTL compiler?

Again, Thanks for your help
Ali