Normally only one polarity of transistor is used to make a current-mirror.I am designing the current mirror (Cascade, improved cascade, Wilson,..) using NMOS and PMOS transistor
HI crutschow,Normally only one polarity of transistor is used to make a current-mirror.
Post a schematic of your circuit so we can understand to what you are referring.
Hi BradtheRad,Your load current goes through a total of 4 transistors in series. That introduces a large amount of unpredictability into the setup. Did you step up to this from the simplest basic current mirror? Then to add one transistor at a time, to see if it performs as you expect?
As for mosfet behavior, I think it's harder to predict what Amperes should flow in one considering the fact they're voltage controlled (via bias voltage) rather than current controlled.
Whereas if you instead were to construct with bjt's, then your results should naturally come from current-controlled behavior. BJT's have direct interaction of bias current with C-E current (and vice-versa), as well as direct interaction between the control 'totem' and the mirrored (load) totem.
Hi FvM,Two complementary current sources driving a floating load don't make much sense at first sight. How does it avoid mid potential running away? Is there a hidden CM feedback circuit? Also, we don't have floating substrates in standard CMOS technology.
Other points are unclear too, how are the cascode gates biased? To understand why you get ro as is, all transistor parameters and bias conditions must be known.
Hi FvM ,All n substrates are tied to Vss and p substrates to Vdd in standard CMOS technology.
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Improved Wilson topology doesn't work well for multiple output current sources. You are paralleling two current sensing diodes, so they can no longer sense the current of individual outputs. Use standard cascade topology.
Hi FvM,Hi FvM ,
First of all, really appreciated your help,
I did tow types of cascode ( standard and improved) as in the attached pictures.
The main reason behind the improved cascode is to maximize the output voltage on the load (RL), less drop on transistors, this is needed in the circuit.
However, for both circuit at I=100uA, when the RL=5K, the ro of the P and N MOS transistors that connected in series with the load (RL) are higher than when RL is 10K!! and this is very confused!!!
Please, when I connect all substrates to (VSS for NMOS and VDD for PMOS), the VDSsat,VGS, Vth are increases, but when I connect as in the attached pictures then these values are not change(seem good) how can I keep these values constant when connect all substrates to (VSS for NMOS and VDD for PMOS)?
Hi dick_freebird,Putting your load between current source and current sink
is asking for disappointment, one will win and one will just
cost you headroom.
The NMOS shown body-tied-to-source is only realizable in
SOI or triple-well CMOS process flavors. Bulk or epi CMOS
generally has a common global psub.
1. You didn't explain how the circuit keeps current sources operating although the load potential is undefined, apparently there's no CM feedback. At least the voltage will shift until the transistors of one current source are only marginally saturated and its output current reduces respectively. Considering that complementary sources have not exactly equal current, this shows as reduced output resistance.You are correct about the sink and source but this is what the circuit is need, it ok for the circuit.
Hi FvM,1. You didn't explain how the circuit keeps current sources operating although the load potential is undefined, apparently there's no CM feedback. At least the voltage will shift until the transistors of one current source are only marginally saturated and its output current reduces respectively. Considering that complementary sources have not exactly equal current, this shows as reduced output resistance.
2. Problem of unsuitable Wilson circuit with two outputs has been addressed. Did you check if standard cascode performs better?
3. Any cascode CS has finite output resistance at the end. It's not clear if your expectations are realistic with given transistor parameters and operation conditions.
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