Out put resistance (ro) of current mirror

[noor84]

Hi,

I am designing the current mirror (Cascade, improved cascade, Wilson,..) using NMOS and PMOS transistor, but unfortunately, as the load (resistance load R=0.5, 1, 1.5, 2, 2.5 ,3, 3.5 Kohm) changes ( increases) the output resistance (ro) is changing (decreases) then the current changing (decreases).

the question is: how can I know the limit changing of the load that keeps the ro almost constant (High) and the current constant?

Note: for example, at RL=1K, the current Id=0.5mA and the ro=1.5M Ohm, but at R=3.5K, the current reached 0.498mA and the ro=140k Ohm. (All transistors operate in Sat at these values)

 

[crutschow]

I am designing the current mirror (Cascade, improved cascade, Wilson,..) using NMOS and PMOS transistor

Normally only one polarity of transistor is used to make a current-mirror.

Post a schematic of your circuit so we can understand to what you are referring.

 

[noor84]

Normally only one polarity of transistor is used to make a current-mirror.

Post a schematic of your circuit so we can understand to what you are referring.

HI crutschow,
Thank you for the reply,

Please, see the circuit in the attached picture.

 

[BradtheRad]

Your load current goes through a total of 4 transistors in series. That introduces a large amount of unpredictability into the setup. Did you step up to this from the simplest basic current mirror? Then to add one transistor at a time, to see if it performs as you expect?

As for mosfet behavior, I think it's harder to predict what Amperes should flow in one considering the fact they're voltage controlled (via bias voltage) rather than current controlled.

Whereas if you instead were to construct with bjt's, then your results should naturally come from current-controlled behavior. BJT's have direct interaction of bias current with C-E current (and vice-versa), as well as direct interaction between the control 'totem' and the mirrored (load) totem.

 

[noor84]

Your load current goes through a total of 4 transistors in series. That introduces a large amount of unpredictability into the setup. Did you step up to this from the simplest basic current mirror? Then to add one transistor at a time, to see if it performs as you expect?

As for mosfet behavior, I think it's harder to predict what Amperes should flow in one considering the fact they're voltage controlled (via bias voltage) rather than current controlled.

Whereas if you instead were to construct with bjt's, then your results should naturally come from current-controlled behavior. BJT's have direct interaction of bias current with C-E current (and vice-versa), as well as direct interaction between the control 'totem' and the mirrored (load) totem.

Hi BradtheRad,
Thanks for the reply,

For my work, I have to work with CMOS technology so I have to use the FET transistor in the current mirror.
Regarding the simple current mirror, I tried a simple current mirror but I didn't get any results then I went to the Wilson and cascade structure to reduce the drop voltage (VDS) on the transistors and to keep most of the drop on the load, but I see more drop voltage (VDS) on the PMOS than NMOS (I don't know why).

Thus, as I wrote :
I am designing the current mirror (Cascade, improved cascade, Wilson,..) using NMOS and PMOS transistor, but unfortunately, as the load (resistance load R=0.5, 1, 1.5, 2, 2.5 ,3, 3.5 Kohm) changes ( increases) the output resistance (ro) is changing (decreases) then the current changing (decreases).

the question is: how can I know the limit changing of the load that keeps the ro almost constant (High) and the current constant?

Note: for example, at RL=1K, the current Id=0.5mA and the ro=1.5M Ohm, but at R=3.5K, the current reached 0.498mA and the ro=140k Ohm. (All transistors operate in Sat at these values).


I hope you can help me.

 

[FvM]

Two complementary current sources driving a floating load don't make much sense at first sight. How does it avoid mid potential running away? Is there a hidden CM feedback circuit? Also, we don't have floating substrates in standard CMOS technology.

Other points are unclear too, how are the cascode gates biased? To understand why you get ro as is, all transistor parameters and bias conditions must be known.

 

[noor84]

Two complementary current sources driving a floating load don't make much sense at first sight. How does it avoid mid potential running away? Is there a hidden CM feedback circuit? Also, we don't have floating substrates in standard CMOS technology.

Other points are unclear too, how are the cascode gates biased? To understand why you get ro as is, all transistor parameters and bias conditions must be known.

Hi FvM,
I really appriciate your help,

the circuit in the attached picture, and the main problem is the ro is decreases as the load RL increases and also ro decreases as the current increase. ( I really need help and explanation why and what's is happening)


Please, what do you mean by 'floating substrates in standard CMOS'?

 

[FvM]

All n substrates are tied to Vss and p substrates to Vdd in standard CMOS technology.

--- Updated Jan 30, 2023 ---

Improved Wilson topology doesn't work well for multiple output current sources. You are paralleling two current sensing diodes, so they can no longer sense the current of individual outputs. Use standard cascade topology.

 

[noor84]

All n substrates are tied to Vss and p substrates to Vdd in standard CMOS technology.

--- Updated Jan 30, 2023 ---

Improved Wilson topology doesn't work well for multiple output current sources. You are paralleling two current sensing diodes, so they can no longer sense the current of individual outputs. Use standard cascade topology.

Hi FvM ,

First of all, really appreciated your help,

I did tow types of cascode ( standard and improved) as in the attached pictures.

The main reason behind the improved cascode is to maximize the output voltage on the load (RL), less drop on transistors, this is needed in the circuit.

However, for both circuit at I=100uA, when the RL=5K, the ro of the P and N MOS transistors that connected in series with the load (RL) are higher than when RL is 10K!! and this is very confused!!!

Please, when I connect all substrates to (VSS for NMOS and VDD for PMOS), the VDSsat,VGS, Vth are increases, but when I connect as in the attached pictures then these values are not change(seem good) how can I keep these values constant when connect all substrates to (VSS for NMOS and VDD for PMOS)?

 

[noor84]

More::
'FvM ': is it possible to connect the substrate for the NMOS to it Source and PMOS to it Source? in this manner these substrates will not be floating and the VDSsat, VGS, Vth will not be high.!!! is this correct?

 

[FvM]

Check the available technology.

 

[noor84]

Hi FvM ,

First of all, really appreciated your help,

I did tow types of cascode ( standard and improved) as in the attached pictures.

The main reason behind the improved cascode is to maximize the output voltage on the load (RL), less drop on transistors, this is needed in the circuit.

However, for both circuit at I=100uA, when the RL=5K, the ro of the P and N MOS transistors that connected in series with the load (RL) are higher than when RL is 10K!! and this is very confused!!!

Please, when I connect all substrates to (VSS for NMOS and VDD for PMOS), the VDSsat,VGS, Vth are increases, but when I connect as in the attached pictures then these values are not change(seem good) how can I keep these values constant when connect all substrates to (VSS for NMOS and VDD for PMOS)?

Hi FvM,
I will search for the teachnology.
But, What about the above?

 

[dick_freebird]

Putting your load between current source and current sink
is asking for disappointment, one will win and one will just
cost you headroom.

The NMOS shown body-tied-to-source is only realizable in
SOI or triple-well CMOS process flavors. Bulk or epi CMOS
generally has a common global psub.

 

[noor84]

Putting your load between current source and current sink
is asking for disappointment, one will win and one will just
cost you headroom.

The NMOS shown body-tied-to-source is only realizable in
SOI or triple-well CMOS process flavors. Bulk or epi CMOS
generally has a common global psub.

Hi dick_freebird,
Thanks for reply,

You are correct about the sink and source but this is what the circuit is need, it ok for the circuit.
Thank for information about the Bulk.


But, please, I am asking about the ro, why is changing as I described in the first comment.

Hope you help for this confuse issue.

 

[FvM]

You are correct about the sink and source but this is what the circuit is need, it ok for the circuit.

1. You didn't explain how the circuit keeps current sources operating although the load potential is undefined, apparently there's no CM feedback. At least the voltage will shift until the transistors of one current source are only marginally saturated and its output current reduces respectively. Considering that complementary sources have not exactly equal current, this shows as reduced output resistance.
2. Problem of unsuitable Wilson circuit with two outputs has been addressed. Did you check if standard cascode performs better?
3. Any cascode CS has finite output resistance at the end. It's not clear if your expectations are realistic with given transistor parameters and operation conditions.

 

[noor84]

1. You didn't explain how the circuit keeps current sources operating although the load potential is undefined, apparently there's no CM feedback. At least the voltage will shift until the transistors of one current source are only marginally saturated and its output current reduces respectively. Considering that complementary sources have not exactly equal current, this shows as reduced output resistance.
2. Problem of unsuitable Wilson circuit with two outputs has been addressed. Did you check if standard cascode performs better?
3. Any cascode CS has finite output resistance at the end. It's not clear if your expectations are realistic with given transistor parameters and operation conditions.

Hi FvM,
Thank you for your reply,

Regarding (1) of your reply:
The RL voltage is defined as the given current, for example, if I= 1 mA from the current mirror the voltage will be 1V on the RL of 1K and so on.

Regarding: "apparently there's no CM feedback"
in the previously attached pictures, there are two types of circuits (standard cascade "no feedback" and improved with feedback).

Regarding "At least the voltage will shift until the transistors of one current source are only marginally saturated and its output current reduces respectively":
Please, which voltage do you mean?

Really the bottom point is important and please may you explain more?
At least the voltage will shift until the transistors of one current source are only marginally saturated and its output current reduces respectively. Considering that complementary sources have not exactly equal current, this shows as reduced output resistance.

Regarding:
Problem of unsuitable Wilson circuit with two outputs has been addressed. Did you check if standard cascode performs better?

In the previously attached pictures there is a standard cascade and the same problem that is:
The issue is that the ro (especially of NMOS transistors in the bottom attached picture, transistor number:1323, 1301)) reduces as the RL change (10 to 10k ) with the same low current or even with a high current (1u to 100uA) passes through RL.


Regarding "Any cascode CS has finite output resistance at the end. It's not clear if your expectations are realistic with given transistor parameters and operation conditions."

I computed the ro approximately as ro=gm(1323)*rds(1323)*rds(1301), this for NMOS, and the same for the PMOS.

1323 and 1301 are the numbers of the transistors in the pictures.


Your notes are very valuable, hope to get a reply from you.