OTA along with class AB output stage

[bharath_k]

Hello Guys,

I need help in designing an Op amp consisting of OTA and class AB output stage. I have come up with circuit in the attachment. Can anyone help me how to go about designing from the second stage?
It would be really helpful.

 

[frankrose]

The output stage is basically an inverter. The gates of the inverter should get in-phase signals, not inverted signals I think, as on your figure.

Oh, sorry, I didn't see the cap, I thought the PMOS is connected to the differential pair's output. Next time please add points to connected nets.
The problem of this circuit that the quiescent current of the output stage will change a lot with supply voltage. Is it a problem for you, the supply dependency?
Other issue is the stability because all of the stages have high gain and will be hard to shift all pole frequencies to get some phase margin and the desired gain bandwidth.
Do you have any specifications?

 

[FvM]

It's no class AB output stage. You should place complementary common drain instead of common source output stage.

 

[frankrose]

It's no class AB output stage. You should place complementary common drain instead of common source output stage.

Actually inverter is a push-pull amplifier. There is a quote from P. E. Allen's book:
"Push-Pull (Class B and Class AB) amplifiers – The current flows in each transistor (M1 and M2) for less than the entire period of a sinusoidal input. Class B is 180° and Class AB is between 180° and 360°."

 

[bharath_k]

Hi Frankrose. I do not have any specifications.

 

[bharath_k]

Yes exactly. I have tried to bias the the inverter by using diode method. Realizing diodes with diode connected mosfets.

 

[frankrose]

MOS diodes can reduce the operating current in the output stage, but still you have a poor supply sensitivity with the inverter output.
And with 3 high gain stages probably it will oscillate, one miller compensation isn't enough, and/or the circuit has to be very-very slow. I assume it shouldn't be slow because the reason of the output stage is to change voltage fast on the Cload.
Sometimes an NMOS source-follower is used as 2nd stage to generate control for the NMOS in the inverter output, because it reduces the operating current, gain is only ~1 and it doesn't add more low frequency poles to the loop. However, that architecture also has a poor supply sensitivity because of the inverter output stage.

 

[bharath_k]

I am planning to design to get a gain of around 30 db from first stage and close to 10 db from next two stages and keep the overall gain around 40db. As the current increases from stage to stage I thought I can control gain and mostly there wont be any dominant poles. I wanted help to select the current levels flowing through M9, M10 and M11 M12.

My task is just to design and analyze this op amp in 22nm tehnology. If there is any other architecture with single stage OTA als would be very helpful.

 

[bharath_k]

Sorry forgot to attach the image of circuit.

 

[frankrose]

I am planning to design to get a gain of around 30 db from first stage and close to 10 db from next two stages and keep the overall gain around 40db

I don't know 22nm, but I can't imagine that an inverter with capacitive load will has only 10dB, and current mirror loaded 2nd stage will has got also only 10dB.

As the current increases from stage to stage I thought I can control gain and mostly there wont be any dominant poles.

Of course you will need 1 dominant pole! With others you will have problems. The frequency difference between neighbour poles should be more decades to get positive phase margin. The current difference will be quite high then because of the higher pole number, and if you don't want too big consumption I assumed your OTA speed will be slow. I think it is not the proper way to solve this.

Until you don't share what do you want (how much is Cload, what slew-rate and UGBW is needed, consumption, in/output voltage range, etc.) I can't recommend you any architecture.

And on your schematic the load of the diff.pair how biased? I think you missed a diode connection on the left side (M3), and why did you post the same but rotated schematic?

 

[bharath_k]

I posted the same circuit with transistor names and yeah I missed a diode connection. Actually they haven't given me any specifications. I am free to choose.

 

[FvM]

And with 3 high gain stages probably it will oscillate, one miller compensation isn't enough, and/or the circuit has to be very-very slow. I assume it shouldn't be slow because the reason of the output stage is to change voltage fast on the Cload.
Sometimes an NMOS source-follower is used as 2nd stage to generate control for the NMOS in the inverter output, because it reduces the operating current, gain is only ~1 and it doesn't add more low frequency poles to the loop.

That's what I say about the output stage. I still believe that it's essentially a drawing error because the MOS diode bias circuit makes no sense for common source circuit.


In addition, I agree that the common source second stage already breaks the OTA topology.

 

[frankrose]

Diodes make sense I think, because they reduce the VgsN0 and VsgP0. Without diode(s) the VgsN0 and VsgP0 is ~VDD/2, and if the VDD varies the Id of the output stage will change more because of the square-law transfer characteristic.
If he place a DC difference between the gates of the CMOS inverter by the diodes, the operating points of the output devices will be shifted on the transfer characteristic to a point where the Id variation is smaller around, and the supply sensitivity is smaller then maybe. That is why I mentioned the source follower 2nd stage, where only the NMOS of the CMOS inverter is connected to the source follower's output, but the PMOS is connected to the input of the 2nd stage. It also adds DC difference between the gates.
I am not sure, and I agree that common-drain class AB would be better but sometimes it is not possible. He probably couldn't get the necessary output voltage swing with that.

 

[bharath_k]

So according to my understanding from your inputs. I have come with the following circuit.

Is the miller compensation necessary? what are the factors I should take into consideration designing second and output stage?

 

[frankrose]

The compensation is necessary, but connect the cap between the output of the diff.pair and the output of the inverter rather. The dominant pole should be set by a high resistive node, not a small like the source follower's output. And the inverter's output is a high impedance node too, so maybe not this is the best way to stabilize the circuit. How large is the Cload??

 

[bharath_k]

I am free to choose Cload. I thought of using 2pF.

 

[frankrose]

Ok. That is not an extreme value at least. Don't you believe a simple 2 stage OPAmp is enough for you? Sorry, but find out the specifications first and find an architecture after that. I can't help you until they aren't clear.

 

[bharath_k]

This is what I am asked to do.

All your inputs have been very helpful. I am trying to design for the architecture with source follower second stage.

 

[frankrose]

You are welcome. I don't suggest to go forward with the source follower 2nd stage, basically it is a bad design because of the current variation, you will have problems with it. I recommend a book which explains better why is it bad, and shows a better class AB output OPAmp with controlled output current, but it still seems risky to me:
R. Jacob Baker - CMOS Circuit Design, Layout, and Simulation - 3rd edition, page 817-819
And P.E.Allen has a good reputation on the CMOS territory, here is a good small guide from him in this topic:
https://pallen.ece.gatech.edu/Academic/ECE_6412/Spring_2004/L060-Push-Pull(2UP).pdf