set clk_1 [define_clock -period 1000 -name clk_1 Clk]
external_delay -input 150 -clock $clk_1 -name input_constraint1 -edge_rise [find /designs* -port ports_in/in* ]
external_delay -input 150 -clock $clk_1 -name input_constraint2 -edge_fall [find /designs* -port ports_in/in* ]
I do find out that if having two constraints on the same input port ( [find /designs* -port ports_in/in*] ) with different names, RTL Compiler will consider the input port changes 150ps after each edge of the clock (both positive and negative edges). That means, if the positive edge of clock is at 0, this input port changes at 150ps and 650ps.
Maybe this is not as useful. RTL Compiler fix setup time only, not for hold time anyway. I need ways to specify these kind of constraints in Encounter during place & route, so that it does setup and hold time analysis correctly for the input port. Anyone?