clock voltages
As far as I understand it..
The original boostrap circuit produces clock voltages that are higher than Vdd (e.g. voltage pumps described in Baker/Li/Boyce CMOS book). The level of the clock on voltage is constant, so Vgs is again signal dependent, although higher than when using normal clock. This approach may cause problems with gate oxide reliabilty.
Modified circuit as described in "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter" by Abo & Gray provides constant Vgs equal to Vdd (so that Vg is signal dependent). They write that such a circuit will not reduce oxide reliability, so it seems that if Vgb will exceed Vdd, it will not cause problems with reliability.
Can someone explain it in the terms of device physics??