I'm using Design Compiler to synthesize a simple arithmetic right shifter in verilog
Code:
out = in >>> shift
"shift" is 5-bits, but I know the max. value "shift" can get is 17 so I don't need the whole 32-bit shifter. How to instruct Design Compiler to synthesize the shifter as just a 17-bit shifter?
Admittedly this requires some intelligence in the synthesizer to understand how to optimize it but my understanding is that a modern synthesizer can do it. You could check the schematic to see exactly what it did.
Another fallback is a 17 case case statement explicitly handling the 17 possible shifts.