I have a simple synchronous parallel bus that connects to the input pins of an FPGA.
The bus consists of the following signals:
1. Data (16 lines)
2. Valid
3. Clock
"Data" and "Valid" are synchronous to "Clock" which runs at 100MHz.
I want my FPGA to serialize the input and send it via an optical wire (SFP).
The receiving side of the fiber is also an. FPGA that does the opposite. I.E extract the clock and the signals synchronous to it.
The extracted clock on the receiving end will be driven into a PLL and used as a system clock.
Can you please suggest a SERDES In core that can connect to the SFP and can be implemented on a Xilinx device?
Clock recovery is the critical task. I'm not aware of respective hardware features with Xilinx FPGA (besides Gigabit receivers with built-in CDR). With Altera, you can use PLL dynamic phase shift to implement a kind of soft clock recovery.
In any case, SFP needs DC balanced data streams, e.g. 8b/10b coded.
Here is something that might interest you as to the feasibility of doing a FPGA (Xilinx V5 in this case) and SFP transmission of data using Aurora protocol.
The example is using Gigabit (GTX) transceivers, a perfect and self-contained solution for high bit rates (e.g. > 600 MBPS). Unfortunately the OP didn't mention the intended speed range.
The SFP's will be selected by according to the throughput requirement...I.E: 16 data bits + 1 control bit + 1 clock signal. This means that the total serial throughput is (16 + 1 + 1) * 100,000,000 = 1.7GHz
Any transceiver of a 7 series FPGA will handle that.
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I've used Aurora 8b/10b before to connect 2 Xilinx FPGAs and it worked well.
However, in both cases - I only had to move data from one side to the other (not a clock...).
Now I want to simply "Mirror" the parallel interface of FPGA #1 to FPGA #2 (including the clock). I don't want to sample the Data and Valid signals in FPGA #1 and move them without the clock to FPGA #2.
The SFP's will be selected by according to the throughput requirement...I.E: 16 data bits + 1 control bit + 1 clock signal. This means that the total serial throughput is (16 + 1 + 1) * 100,000,000 = 1.7GHz
The calculation is different. 16 data bits with 8b/10b coding makes 20 serial bits. You need at least 2 GHz for 100 MWords/s. The clock is already embedded in the data stream. Data gaps can be marked by 8b/10b idle characters.
Now I want to simply "Mirror" the parallel interface of FPGA #1 to FPGA #2 (including the clock). I don't want to sample the Data and Valid signals in FPGA #1 and move them without the clock to FPGA #2.