Opencores DDR SDRAM Controller help !!!

[cippalippa]

Hi,

I try to use the Opencores DDR Controller; I simulate the core and work well.
Now I try to implement the IP in the Spartan3E Starter kit but the controller don't work; may I know if sameone have already used this IP?
May I know if sameone have documentation about this core?
Otherwise, is the DDR IP generate with Xilinx Memory Interface Generator easy to use?
Thanks in advance for all.

Daniele

 

[anmolvlsi13]

use other devices of Spartan2 Kit.
Anmol

 

[rakesh_aadhimoolam]

Hi cippalippa

it would be grt if you post the code for the controller b'cos i don't find the code on opencores

plz do so....

thanks

 

[nmurthy]

try xilinx core generator if available and if possible
hope that works without any problem

 

[vinod_g]

Depending upon the XLINX or ALTERA u got a lot of specifications on their website and u can use these as IP cores. U can also search in the MEGACORE ,u have detail in this website

 

[cippalippa]

Hi,

I found some error in my ucf file, so now the controller working well in my Spartan 3E board.
The only things is that this core is for ea 256 Mbit DDR SDRAM but I have a 512 Mbit; may I know if sameone have already modified the code in order to increase the memory?

For the Xilinx MIG I asked at the FAE if the DDR SDRAM core generated for the Spartan 3E is working and he say me that is not sure.

Daniele