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Opamp offset in BandGap Reference

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ethan

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bandgap offset

Hi there,

I am wondering whether anyone can guide me for the following questions. Appreciate your help.

1. The first one is a naive question, I forgot why CMOS diff-pair opamp always has very larger DC offset, comparing with bipolar-diff-pair opamp?

2. Why opamp offset is one critical point when designing BandGap reference? especially if we want to do curvature compensation. From the literature, i know that we need the offset of the opamp to be as low as possible.

3. If my current technology can make only diode and CMOS, is there any technique I can use to reduce opamp offest without using bipolar input diff-pair?
I only know there are techniques called auto-zero and chopper techique to apply to ADC(especially Switched-capacitor ADC with CDS technique or Chopper), but I am not quite familiar with auto-zero technique for continuous operation which directly apply to opamp itself. Can anyone give me some links of reference literatures.

4. I read many published papers about curvature compensation techniques for BGR. But any people can tell me whether, in current industry, the designers or companies did implement curvature compensated BGR circuit in their chips or not?
 

keiichi451

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op amp temperature dependent offset

I am working on something similar... These answers are based on my limited knowledge. Please feel free to add/comment on my input.


1. Offsets are worse in CMOS because :
(a) MOS Offset is a function of threshold mismatch, which does not occur in BJTs.
(b) MOS Offset scales with overdrive voltage rather than Vt (26mV for BJTs), this is typically a larger value, in the hundreds of mV.


2. Your opamp's offset will be amplified, shifting your output DC level (error). Even if you compensate your curve, you reference voltage will be different from what you projected. Also, CMOS amplifier offset is itself temperature dependent, raising the temperature coefficient of the output voltage.

3. Look into "dynamic offset stablization techinques" using "feed-forward topologies" if you need continuous signal paths.
 

    ethan

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ethan

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Hi keiichi451,

Your reply is very clear to me.

I am wondering that whether you are willing to upload some reference literatures regarding you mentioned "dynamic offset stablization techinques" using "feed-forward topologies", if you think it is very useful and in hand? Appreciate your help.


keiichi451 said:
I am working on something similar... These answers are based on my limited knowledge. Please feel free to add/comment on my input.


1. Offsets are worse in CMOS because :
(a) MOS Offset is a function of threshold mismatch, which does not occur in BJTs.
(b) MOS Offset scales with overdrive voltage rather than Vt (26mV for BJTs), this is typically a larger value, in the hundreds of mV.


2. Your opamp's offset will be amplified, shifting your output DC level (error). Even if you compensate your curve, you reference voltage will be different from what you projected. Also, CMOS amplifier offset is itself temperature dependent, raising the temperature coefficient of the output voltage.

3. Look into "dynamic offset stablization techinques" using "feed-forward topologies" if you need continuous signal paths.
 

keiichi451

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Here are a couple papers on the topic of offset cancellation. There were many more, but these should give you a good start.
 

keiichi451

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For some reason, I can't attach the 2nd file... Is it too large? (It's only 2.6MB)

If you have IEEExplore, look up "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization" by Christian Enz, it was published I think 1996.
 

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