Opamp common mode voltages for ADC

[moisiad]

Hi

In a pipeline ADC the OPAMP must be designed to have an input and output common mode voltage equal to VDD/2? Or we dont care as it operates in a closed loop with a gain equal to 2.

 

[sunking]

Mostly it is near VDD/2. But you can use other value to meet your requirement

 

[wangyuxin]

what about the output common mode varys clock by clock?

 

[gingerjxb]

in general, the output common-mode voltage of opamp is set to vdd/2 in order to hold large dynamic range, while the input common-mode voltage is set based on your requirement, as sunking said, for example, it isn't set to vdd/2 when in low-voltage application

 

[wangyuxin]

in general, the output common-mode voltage of opamp is set to vdd/2 in order to hold large dynamic range, while the input common-mode voltage is set based on your requirement, as sunking said, for example, it isn't set to vdd/2 when in low-voltage application

what i mean was the output common mode voltage not settling in the same value cycle by cycle,that is ,the output common mode voltage settling value differ about 10mv clock by clock.

 

[gingerjxb]

hi wangyuxin

you mean the common-mode voltages of sampling phase and hold phase are different? are you using single-end architecture? maybe it's because of charge injection. can you upload your circuit and simulation results?

 

[wangyuxin]

hi wangyuxin

you mean the common-mode voltages of sampling phase and hold phase are different? are you using single-end architecture? maybe it's because of charge injection. can you upload your circuit and simulation results?

i use a differential architecture, the SH circuit is a traditional fold-cascode with single-end gain-boosting,i will put my simulation result here recently.

 

[shaokang_w]

you can put 2 outputs to vdd/2 by TG in half of clock

 

[laglead]

precise commond mode voltage is not a must.

 

[stuck_adc]

inoder to make the circuit operate faithfully we need to bias the ckt properly and for that matter we need to fix the operating point of the circuit. ideally common mode voltages should be vdd/2 as this provide the best operating conditions for the circuit.

if the operating point is set to a appropriate value then we will get a very good gain when seen in the ac analysis.

so just give it a try and see the results in the ac analysis:-
1) fixing the common mode voltage as vdd/2
2) setting somewhere far from vdd/2.

i am very sure you will be able to see the remarking difference in both the results

and you will get your answer.