OPAMP 2-stages design problems

[ldhung]

I designed an opamp unbuffered 2 stages, but there are the shifts between input and output. Please help me to adjust the output has the same offset is zero as input.
Please see the photos for more details.
Thanks

 

[Bus Master]

Hi,

As i understand, your waves are totally in-phase, and your problem is that the O/P swings around 100mV while the I/P signal swings around 0V.

The De-Coupling capacitor Cc is responsible for blocking I/P DC value so your O/P voltage will swing Freely around the O/P stage Quiescent voltage value.
Did you try changing the V_Bias to a lower voltage? Try this while applying 0V to your I/P. I think this is the point where solution will be around.

 

[jgk2004]

Hello,

If you make your second stage have the same current in it as your first stage( one side of the diff pair) your offset will go away. So if your first stage tail current is 10uA make your second stage have 5uA. What this does is makes your current mirror in your first stage match your second stage Vds. Also you should have all three of the PMOS transistors the same W and L. If your playing the game of increasing the second stage PMOS W to increase the open loop gain, it will create offsets and also make your amplifier not function properly, so dont do that!

hope this helps
Jgk

 

[checkmate]

What you need to measure is the input-referred offset. Open loop offset will easily be whittled down by the high gain once it is in closed loop configuration.

 

[ldhung]

I find out that the offset shift is 10mV is typical around the technology. Anyway, thanks so much, especially jgk2004.
@jgk2004: I will pay attention to your comment. Thank so much