ghattas.akkad
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Hello guys!
i have implemented the following online adder for signed digit using vhdl code
and i have simulated my design according to the example table shown in the figure attached
the problem is i am not getting the first result which is "10" for Z+ and Z+ and at some point a combination of XX and YY gives different ZZ
i also did not understand the happening operation since if i normally add the given bits
i do not obtain the same result
is there a special conversion happening?
i have implemented the following online adder for signed digit using vhdl code
and i have simulated my design according to the example table shown in the figure attached
the problem is i am not getting the first result which is "10" for Z+ and Z+ and at some point a combination of XX and YY gives different ZZ
i also did not understand the happening operation since if i normally add the given bits
i do not obtain the same result
is there a special conversion happening?