one transistor forward converter...or flyback?

[Orson Cart]

Hello Manuele, if what you say is true then all ZVS topologies would have markedly higher losses than they do - in fact if you turn off the gate fully and rapidly (in <40nS say) then the drain current ceases and the current transfers to the inherent D-S capacitance (which is largely lossless) - every resonant converter with ZVS exploits this fact. The effective Vds during channel turn off is therefore very low and it is easy to see this on a good oscilloscope, where the gate gets to zero BEFORE the Vds starts to rise, of course if the gate drive is not good enough (too slow and too high impedance at the edge frequencies) you will not get this effect.
Regards, Orson Cart.

 

[macubo]

Hello Orson, first of all thank you for clarifying things with me.
Second, we are perhaps going off topic.

I think that what you say is true at turn-on. Turning-on in ZVS, like in LLC resonant, or BCM flyback with Vreflected>Vrect, clearly cancels out switching losses associated to overlap in current-voltage. You see this even on the gate waveform, where the Miller plateau fades away, right?

At turn-off, just the LLC retains the ZVS, as the current is ricirculating in 3rd quadrant thru the inherent diode. But in flyback, current is "high" at turn-off. I think you could probably speed up the gate drive as much as you can, but must anyhow remove the associated Qgd charge and Miller plateau shows up again.

With a 500MHz DSO scope, I've never seen the gate touching zero before Vds starts to rise on a flyback. If you have seen that, and if you were using external current probes, can you exclude that its amplifier wasn't delaying the signal to the scope (talking about tens of nsec that could be the case)?

Bye, manuele

 

[Orson Cart]

In an LLC the fets turn off with high current, just as a flyback does, and the turn off losses are near zero, sometimes the fet capacitance is added to with an external cap.
You don't need a current probe to see the Vgs reach zero before the Vds starts to rise - simply a low impedance, high current, turn off gate drive, and a proper scope with properly connected and compensated leads. If the Vds starts to rise before the fet Vgs reaches zero it implies the gate drive is simply not up to the task. Some people don't mind a slower turn off as it lessens the Vds overshoot if you have a high leakage transformer - but if you want max efficiency then a proper gate drive is the way to go.
Regards, Orson Cart.

 

[macubo]

In an LLC the fets turn off with high current, just as a flyback does

You are right, my mistake I was probably thinkin about turn-on

You don't need a current probe to see the Vgs reach zero before the Vds starts to rise

You are right again, oh gosh what the hell I was think to?

Some people don't mind a slower turn off as it lessens the Vds overshoot if you have a high leakage transformer - but if you want max efficiency then a proper gate drive is the way to go.

I agree completely, but this way we are almost certainly increasing CM noise. I still don't get the point of null turn-off losses, but it's probably a limit of mine.
Bye, manuele