one dimensional array in vhdl

[jincyjohnson]

How can i store values in a ID array, if each location store multiple bits.
ex:[1001, 1010,1111]
These number of bits and number of locations are variable.The values stored are the output of a variable length circuit which can be set by the user. plz reply

 

[ads-ee]

As your question is vague I'm not entirely sure if you mean the number of bits and locations are variable when in operation or can be set differently at synthesis/compile_time. These two options have entirely different requirements.

Regards

 

[Fahmy]

reg [3:0] A [0:2] ; // declaration for an array A with 3 elements , each element is a 4 bits.

A[0] = 4'b1001 ; // assigns first element in array A to 1001
A[2] = 4'b1111; // assigns third element in array A to 1111

 

[jincyjohnson]

actually i have an n bit johnson counter and m bit seed vector.The johnson counter outputs q0 to qn is xored with seed bit so and stored in first location of array.ie.first location contains n bits.then q0 to qn xored with s1 and stored in second location.this repeats for all the seed bits.how this can be coded in vhdl.plz reply

 

[ads-ee]

Once again I'll ask the same question. Is your 'n' defined while the HW is running or is this a constant defined for synthesis/simulation. These two options will require significantly different implementations.

Regards

 

[jincyjohnson]

n and m is defined in the program using generic

 

[ads-ee]

your definition of what you want to do is somewhat vague in post #4, so I'll attempt to interpret what you specified and fill in the blanks with guesses.

well then you define the signals using the generics

---

Code VHDL - [expand]
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signal SEED : std_logic_vector(0 to m-1);
signal JC : std_logic_vector(n-1 downto 0); 
type ID is array (0 to m-1) of std_logic_vector(n-1 downto 0); -- assuming the number of seed bits define the array depth
signal out_data : ID;
 
-- use a for loop to compute each value in the array
for i in 0 to m-1 loop
  out_data(i) <= JC XOR SEED(m); -- not really sure this is what you described in post #4, but it might give you an idea.
end loop;

---

There's probably some VHDL coding errors as I nearly exclusively use Verilog.

Regards

 

[jincyjohnson]

thnks a lot

 

[jincyjohnson]

is this format used in verilog (post #3)

 

[jincyjohnson]

the code is written as follows.But i didn't get the output.can u check it

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity andg is
port(a,b:in std_logic;
c:out std_logic);
end andg;
architecture aandg of andg is
begin
c<=a and b;
end aandg;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xorg is
port(f,g:in std_logic;
h:out std_logic);
end xorg;
architecture axorg of xorg is
begin 
h<=f xor g;
end axorg;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity df is
port(d,clk:in std_logic;
q:inout std_logic);
end df;

architecture Behavioral of df is
begin
process(clk)
begin
if(clk'event and clk='1')then
q<=d;
end if;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jj is
GENERIC(n:integer:=3;m:integer:=2);
	 port(
	    clk : in STD_LOGIC;
		 rjmode,init:in std_logic;
		 s:in std_logic_vector(m downto 1):="10";
		 q : inout STD_LOGIC_vector(n downto 1):="111");
end jj;

architecture counter of jj is
type memory is array (0 to m-1) of std_logic_vector(n-1 downto 0);
signal store:memory:=(others=>(others=>'1'));
signal rwp:STD_LOGIC_vector(n-1 downto 0):="001";
signal cwp:STD_LOGIC_vector(m-1 downto 0):="01";

begin
	process(clk)
	begin

   if(clk='1' and clk'event )then
		
			if(rjmode<='0')then    --for johnson codeword generation .if rjmode=0, a johnson codeword is generated
			q(1)<=not q(n);
		
			end if;
		for i in 2 to n loop
		 q(i)<=q(i-1);
		end loop; 
	   	 for p in 1 to m loop       --loop for seed bits
			 for i in 1 to n loop         --loop for johnson codewords
			 store(conv_integer(rwp))(conv_integer(cwp))<= q(i) xor s(p);   --for xor ing johnson codewords and seeds
			 cwp<=cwp+'1';
			  end loop;
			 cwp<="01";
			  rwp<=rwp+'1';
			  end loop;
			  end if;
   end process;
end counter;

 

[imbichie]

Hi Jincy,

You are not getting the output means, is there any error in the code, if so please post the error message.

When i go through the code i found "if(rjmode<='0')then", i didn't get what its means?
If you wants to check whether the rjmode is '0', just do like this if (rjmode = '0') then.

If there is no compilation error please attach the waveform or explain the unexpected behavior of the logic that you identified.

One another thing is that, if you wants to use the AND or OR or NOT or XOR, etc operators, no need to create the entity again, you can directly use it.

Same for D Flip Flop also. Also you should take care if you are using the inout ports

 

[jincyjohnson]

THE modified code, circuit diagram and waveform is attached below.but the result is wrong


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xorg is
port(f,g:in std_logic;
hut std_logic);
end xorg;
architecture axorg of xorg is
begin
h<=f xor g;
end axorg;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity df is
port(d,clk:in std_logic;
q:inout std_logic);
end df;

architecture Behavioral of df is
begin
process(clk)
begin
if(clk'event and clk='1')then
q<=d;
end if;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jj is
GENERIC(n:integer:=3;m:integer:=2);
port(
clk : in STD_LOGIC;
s:in std_logic_vector(m downto 1):="00";
q : inout STD_LOGIC_vector(n downto 1):="111";
rwp:inout STD_LOGIC_vector(1 to n):="000";
cwp:inout STD_LOGIC_vector(1 to m):="00");
end jj;

architecture counter of jj is
type memory is array (n-1 downto 0) of std_logic_vector(m-1 downto 0);
signal store:memory:=(others=>(others=>'1'));
begin
process(clk)
begin
if(clk='1' and clk'event )then
q(1)<=not q;
for i in 2 to n loop
q(i)<=q(i-1);
end loop;
for i in 1 to n loop
for p in 1 to m loop
store(conv_integer(rwp))(conv_integer(cwp))<= q(i) xor s(p);
rwp<=rwp+'1';
end loop;
rwp<="000";
cwp<=cwp+'1';
end loop;
end if;
end process;
end counter;