one clocked process + one combinatorial process

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promach

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For https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/tx_port_channel_gate_128.v#L95-L107 , are there any reasons to use one clocked process + one combinatorial process ? Will a single clocked process work less better in real hardware implementation ?

Code Verilog - [expand]
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always @ (posedge CHNL_CLK) begin
    rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
    rChnlLast <= #1 _rChnlLast;
    rChnlLen <= #1 _rChnlLen;
    rChnlOff <= #1 _rChnlOff;
end
 
always @ (*) begin
    _rChnlTx = CHNL_TX;
    _rChnlLast = CHNL_TX_LAST;
    _rChnlLen = CHNL_TX_LEN;
    _rChnlOff = CHNL_TX_OFF;
end
 

Its a style some designers use (and used to be mandated by synthesisors many many years ago).
One is not better than the other (but both have pros and cons).
 

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