on set clock latency

[erik_xfan]

set clock latency in DC

Assume that we have a top-level design TOP, which consists of two subdesigns A and B. A clock signal CLK is defined in TOP. Can we specify the clock propagation delays, from CLK to the flipflops in A and B, respectively, which are different from each other?

Solutions on RTL or netlist are both OK!

Thanks a lot!

 

[rca]

during the synthesis, the clock is considered as "ideal", no clock tree available so only the margin added by clock uncertainty is used by the tool.