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On Chip Termination Cyclone IV FPGA

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flote21

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Programable Termination resistance Cyclone IV FPGA

Hello people!

I am generating a 150 MHz clock with a 3.3V-LVTTL I/O FPGA pin and I want to know if it is possible to programm a internal source resistance of 50 Ohm to avoid reflections and other issues. If this is not possible then, I would like to know which the default Zo of the I/O pins.

Thanks!
 

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The information you are asking for "if it is possible to programm a internal source resistance" is what is described in the PDF you posted. What is your question?
 

Yes that is my question. As you can see in the pic attached it is possible to select a output termination in the pin planner of quartus ii. But reading the PDF is not clear if this option applies to I/o 3.3-v-lvttl. Can you clarify this please?

Thanks
 

Capture.JPG

It's right there in the document. NO you can't. See the horizontal lines in the boxes under Rs OCT blah blah? It's pretty clear to me.

If you require OCT then use a 3.0V standard. Most receivers for 3.3V LVTTL will have no problem with 3.0V driving it as there is still adequate margin at the high logic level.
 

My view on OCT is that it's just another way of using programmable drive strength. The fact that Altera doesn't specify OCT settings for Cyclone IV 3.3V IO-standards doesn't mean that you can't use the programmable drivers to match load impedances in a certain range.

The problem is that Altera seems to discourage you permanently to use 3.3V IO with newer FPGA families at all and doesn't provide more than bare necessities to support it. This is due to the small overvoltage margin which can be easily exceeded when e.g. connecting unterminated transmission lines, and probably also the risk of damaging output transistors by drawing excessive current. So output currents available with 3.3V VCCIO have been cut on purpose since Cyclone III.

If you aren't driving too many IO lines, an additional external series resistor should be considered to adjust the total driver impedance.
 

But there is one issue that I forgot to comment. The clock is a single ended signal and the FPGA bank is supplied with 3.3v. Maybe it is not working your solution...
 

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