On-Chip MOS power decoupling cap sizing (urgent)

[sharkies]

Hi guys,,

what's the usual mos decoupling unit cap size you use for your onchip power decoupling?
I understand that depending on the W/L size, gate resistance changes and there's an optimum size to de-Q inductance ringing. I'm in a real crunch and unfortunately don't have time to think through all that.
what W/L sizes do you usually use for your unit cap before you instantiate an array of them?
Currently the design is working on the order of ~hundred MHz. (under 500MHz)
I'm using High voltage mos to minimize leakage. It seems like I have a LOT of extra space to fill in with decoupling.

Thanks, as always

 

[dick_freebird]

I fill all the white space I can, before doing density fills.
I use fingers 10/4 to 20/5, wider than long, and overplate
the poly gate with S/D Met1 for some additional higher-Q
plate capacitance. I count on the poly resistance to do
a "good enough" de-Qing job (I tend to use a process
with unsilicided poly for most of my work).

There's not often such a thing as too much decoupling.
Though somebody will probably b!tch about thin ox area
and defect density.

 

[kenambo]

Hi,

You can find the value of MOS cap values for various devices you use.. then you can use according to the schematic requirement...