On-Chip Clock logic (macros) placement during Testability insertion

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Nanda_DFT

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Is on-chip test clock domain logic (macros) placed before clock domain root or after clock domain root?
 

Is on-chip test clock domain logic (macros) placed before clock domain root or after clock domain root?

Yes and no and neither and both. You can have a test clock that is external to the chip, and doesn't come from any macro at all. You just mux it at some point. You can have a test clock that comes from the same PLL as the system clock and shares the exact same clock tree.
 

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