OFFSET constraint in Xilinx ISE 4.2i

[kala]

Hello,

I'm using Xilinx ISE 4.2i and i've a OFFSET constraint for an input signal in my UCF

NET "p2_din" OFFSET = IN 10 ns BEFORE "p2_clk";

i'm expecting p2_din to be valid atleast before 10 ns before the rising edge of the clock signal p2_sck, but the tool reports that 0.403 ns is the actual value. What does it mean?

thanks in advance,
Regards,
Karthik.