Odd (to me) Verilog schedualing behavior

[beeflobill]

While working on a project I found an odd Verilog simulation behavior that I wasn't expecting. I thought it was interesting because it was so unexpected to me, and I thought that others might appreciate a ( at least a useful ) reminder of what seems to be subtle Verilog behavior. I do have a couple of questions, what is the technical name for this behavior (if there is one), and is this sort of thing simulator specific or firmly set?

I ran the code below and obtained the output:

a=x b=0
a=1 b=0
a=1 b=1
a=1 b=1​

I was really expecting to see something like:

a=1 b=0
a=1 b=0
a=0 b=1
a=1 b=0​

because I was I thought 'a' would immediately update from the assign statement, but I see that the assign statement isn't updating until the end of the timestep.

module bench();

reg b;
assign a = ~b;


initial begin
   b = 0;
   $display("a=%b b=%b", a, b);
   #10;
   $display("a=%b b=%b", a, b);
   b = a;
   $display("a=%b b=%b", a, b);
   b = a;
   $display("a=%b b=%b", a, b);
end

endmodule

Thanks

 

[tariq786]

open the waveform and see whats happening at a particular time. This will help you debug

 

[FvM]

but I see that the assign statement isn't updating until the end of the timestep.

Yes, that's how sequential blocks work.

 

[dave_59]

Both the actual output and what you expected are correct. You could get either depending on what level of optimization is turned on.

The reason is because the initial block and the continuous assignment statement are two independent processes. There are no delays between the procedural assignment to b and the $display statement. When updating the value of b , that causes the continuous assignment to a to execute. You wind up with a zero-delay race between the execution of the $display statement and the update to a. The simulator is free to choose either statement to execute first.