1.) you aren't using a UCF file.
2.) you have a UCF file, but it's not included in the project.
3.) you have a UCF, but have used "TNM" instead of "TNM_NET". one pushes through the input buffer, the other doesn't.
4.) you have mixed case in the UCF, but not in the HDL. While VHDL is not case sensitive, the UCF file is a bit more tricky.
5.) your HDL has counter logic that has async inputs that are used. Such logic can always fail, but can fail always in some implementations. This is particularly true when the user uses fabric resources to derive other clocks.
6.) the pads are not defined in the UCF.
keep in mind that digilent has horrible reference designs (in general). If you've used their code as a reference, you might just be seeing the effects.