tompoh
Newbie level 2
Greetings.
I have designed logic circuitry that has 12 channels with 12 square wave signals at some arbitrary user defined frequency through frequency division by means of a counter and extra circuitry. These 12 frequency division units are connected to the same clock. I implemented this circuit on the old Nexys boards and it works fine with no problem. I have had to purchase a nexys2 on which I have implemented the same design. Strangley on the Nexys2 I get odd results, sometimes the output frequency on one to three channels being twice, three times and even half the expected frequency while being ok on the rest of the channels (The channels have identical circuitry ). If I implement the design with different constraints the problem shifts to different channels. I do not understand what is happening and to be honest, it does not make much sense.
Does anyone have some ideas.
I have designed logic circuitry that has 12 channels with 12 square wave signals at some arbitrary user defined frequency through frequency division by means of a counter and extra circuitry. These 12 frequency division units are connected to the same clock. I implemented this circuit on the old Nexys boards and it works fine with no problem. I have had to purchase a nexys2 on which I have implemented the same design. Strangley on the Nexys2 I get odd results, sometimes the output frequency on one to three channels being twice, three times and even half the expected frequency while being ok on the rest of the channels (The channels have identical circuitry ). If I implement the design with different constraints the problem shifts to different channels. I do not understand what is happening and to be honest, it does not make much sense.
Does anyone have some ideas.