xuexucheng
Full Member level 2
Hello everyone,
I met a very wired problem. I use a Xilinx virtex II FPGA(x2v3000).
There is a internal signal that should be 0 when power on, but when power on this signal occasional is 1 for a clock cycle. This could happen about 1 time every 20 times power on. The below is the FPGA edtor result. The D terminal of the flipflop is globle 1, the ck is globle clock, the SRLOW terminal is controlled by other signals. And the reset type is synchronous. I connect the internal signal to IOs to monitor using osciloscope. I fine the SRLOW is 0, but there maybe 1 at the output of the flipflop. I also put the code in different FPGA board. The result is same. This is a very hard problem. Any reply is welcome. Thanks in advance.
I met a very wired problem. I use a Xilinx virtex II FPGA(x2v3000).
There is a internal signal that should be 0 when power on, but when power on this signal occasional is 1 for a clock cycle. This could happen about 1 time every 20 times power on. The below is the FPGA edtor result. The D terminal of the flipflop is globle 1, the ck is globle clock, the SRLOW terminal is controlled by other signals. And the reset type is synchronous. I connect the internal signal to IOs to monitor using osciloscope. I fine the SRLOW is 0, but there maybe 1 at the output of the flipflop. I also put the code in different FPGA board. The result is same. This is a very hard problem. Any reply is welcome. Thanks in advance.