FvM is indeed a giant! So brilliant!Most FPGAs have power on reset to known state, Virtex II surely has. But in case a clock is already applied during power-on reset, you may need to implement a dedicated asynchronous reset which is released synchronous to the clock, otherwise the POR end may involve a hold time violation.
The only explanation I can see is a timing violation between "CK" and "SR". Can you describe the logic that drives "SR"?
Can "SR" be guaranteed to be '1' when the first "CK" transition occurs?
Have you measured "CK" and "SR" at the same time with the oscilloscope?
Please show the involved source code.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 signal soft_start : std_logic := '0'; process(clk) begin if rising_edge(clk) then if s_start='1' and s_start_cmd=b"111" then soft_start<='1'; soft_stop<='0'; elsif s_stop='1' and s_stop_cmd=b"111" then soft_start<='0'; soft_stop<='1'; else soft_start<='0'; soft_stop<='0'; end if; end if; end process;
do s_start and s_start cmd also have initial values of 0? are they async reset?
The code for for assigning values to s_start and s_start_cmd is too many. I think the problem is not caused by s_start and s_start_cmd, because I test them using oscilloscope. They are keep '0' when there is problem.Please show also the code for assigning values to s_start and s_start_cmd.
Are s_start and s_start_cmd generated by registers or combinatorial logic?
If registers, is it the same clock as for creating soft_start?
What is the clock frequency?
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