https://www.google.com/search?q=NPN+"hot+carrier"
Most detailed papers are copyrighted but persons unconcerned
about this can find interesting yet accessible papers amid the
pay-wall hits. One such is the paper by Hu from Berkeley, it
has beta-vs-Ic curves for varying time*current stress and
physics explanations.
https://www.google.com/search?q=zener+zap+emitter+base
turns up similarly many "pay me for somebody else's work"
pay-wall papers, and some you can get at regarding the
prospect of E-B shorting at higher reverse currents.
Of course every transistor has its own HCE sensitivity
(based on close-in base oxide / interface qualities)
and its own "programming" threshold (for example a
transistor with tri-metal pad-stack on the emitter, will
have a much higher local-damage-temperature-threshold
than one with a plain aluminum metal up against the
silicon (barrier-metal contact FTW).
On the circuit side there is also the question of the
application care-abouts. Of course a resistive E-B short
is going to be pretty universally bad. HCE damage may be
subtle enough to miss in an emitter follower output with
loose tolerances and no "delta" type reliability testing.
For a while. But as some papers show, the damage is
cumulative and if caused by normal power cycling, a
field failure population potential exists.