If the clk is not running-it shows a pop up error :- Core clock either too slow or not connected.If nothing happens, probably the clk is not running. Is both ila share the same clk?
.
Another possibility is to include the default debug core from the MIG. When generating the MIG, you can add the debug core to the memory core.
I hope that it helps.
Are you sure app_rd_data_valid is being sampled in the ILA with the correct clock domain?
The signal is being sampled with correct clock domain but that trigger condition never meets,so that issue is present.My query about lack of hour glass icon might be - that the logic analyzer has finished the process of collecting data,so i'm not seeing the icon.
The thread is being kept alive as i am waiting for Tetik's reply to post# 4
This was the topic of thread,on pressing ila option on both ILA hardware dashboards,the first ila was giving waveform & the second wasn't ?This might seem like I'm treating you like you don't know anything, but that's not the intention...
Did you start both ILAs? You need to press the run trigger on both ILA tabs, otherwise they won't both be running at the same time.
Each ILA will trigger and open it's own waveform window.
I just saw my reply in post #6,i meant that trigger condition(APP_RD_DATA_VALID = '1') was not being met,so it's not getting asserted to '1' & remains '0',so no waveform is being plotted.The signal is being sampled with correct clock domain but that trigger condition never meets,so that issue is present
I just saw my reply in post #6,i meant that trigger condition(APP_RD_DATA_VALID = '1') was not being met,so it's not getting asserted to '1' & remains '0',so no waveform is being plotted.
So this seems more like there is a design problem and the APP_RD_DATA_VALID doesn't go active. Have you run a simulation of the design or did you just jump right into debugging on hardware (I assumed you had run a simulation of the design)?
I would probably run the example design simulation and concentrate on looking at how the app_rd_* side signaling protocol, and compare that with your design. I suspect you'll find a difference in the protocol between the two.
You did run the simulation with a DDR3 model, right? It didn't report any problems, correct? And you read back the values you wrote?
My guess is the DDR3 didn't calibrate for some reason. (resets/power/dci/io/constraints/etc...) You can see your attempt to write because you generate it. It didn't sound like you probed further down to see if it actually worked.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?