moonnightingale
Full Member level 6
I am using Spatran 3E. I have made a code to capture the data packets on ethernet port. I am using the clock of ethernet port which is 25 MHZ but i am not getting the result. When i checked the clock output on Chipscope, it have a constant high level of 1. then I checked the UCF and i have used the exact same statement of manual
NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
When i check the Board clock of 50 MHZ FPGA, i get the clock on Chipscope whcih is perfect.
Why my ethernet clock of 25 MHZ is not working. How can i cross check, is there any probability that my crystal is Unserviceable. Kindly tell me some technique to check that my crystal is generating clock.
Secondly if i use clock of 50 MHZ with ethernet,, what will be the effects.
Why we are having special clock for ethernet. Why cannt it use Board Clock
NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
When i check the Board clock of 50 MHZ FPGA, i get the clock on Chipscope whcih is perfect.
Why my ethernet clock of 25 MHZ is not working. How can i cross check, is there any probability that my crystal is Unserviceable. Kindly tell me some technique to check that my crystal is generating clock.
Secondly if i use clock of 50 MHZ with ethernet,, what will be the effects.
Why we are having special clock for ethernet. Why cannt it use Board Clock