You can increase it for either style by just adding more
inverter-pairs (buffers), and for longer non-overlap by
interposing some RC network (or weak inverter plus dummy
load) in the delay chains. Active and passive approaches
each have their own sensitivities (P, V, T). How much
consistency you require will determine how elaborate
you end up, in the design (less than +/- 50% PVT may
require a stable reference with appropriate tempco and
maybe even a trim against process). Or, if you have a
master clock, you could make a replica DLL to get a
controlled-bias inverter to give you a fixed delay, at
a larger cost in complexity.