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| `timescale 1ns/1ps
module test;
reg clk = 0;
initial begin
// 20 ns clock period (timescale is set to 1ns)
forever #10 clk = ~clk;
end
reg [7:0] a = 3;
reg [7:0] b = 2;
reg [7:0] c = 1;
reg [7:0] d;
always @(posedge clk) begin
b <= a + a;
# 5 c <= b + a;
# 2 d <= c + a;
end
initial begin
// don't make run on statements on one line....
// begin a = 3; b = 2; c = 1;
// this is bad coding style IMO, make it harder to read
// at a glance.
//
// assign a at time 0 same as intial values in declaration above.
#1 a = 3;
repeat (4) @(posedge clk);
// change a to something else after 4 clocks
#1 a = 5;
end
initial
$monitor ("%t - a = %d, b = %d, c = %d, d = %d", $time, a, b, c, d);
// without delays
reg [7:0] e = 3;
reg [7:0] f = 2;
reg [7:0] g = 1;
reg [7:0] h;
always @(posedge clk) begin
f <= e + e;
g <= f + e;
h <= g + e;
end
initial begin
e = 3;
repeat (4) @(posedge clk);
e = 5;
end
initial
$monitor ("%t - e = %d, f = %d, g = %d, h = %d", $time, e, f, g, h);
endmodule |