Non-Blocking: Inter-Assignment Delay

[anilineda]

Hi,

How one will write the port declarations, i tried in various way but it shows error, below is a given code to understand inter assignment delay in non-blocking. i want to see it in simulation. i know delays mentioned here is not synthesizable.

always @(posedge clk) begin
	b <= a + a;
	# 5  c <= b + a;
	# 2  d <= c  + a;
end
initial 
begin a = 3; b = 2; c = 1; 
end

 

[ThisIsNotSam]

I don't understand. Port declarations? Which ports?

The example is also not complete, it is not possible to determine what happens to clock and how fast it is ticking.

 

[FvM]

Why port declarations? You don't need it to test the code, just make it part of the test bench. You however need to know and declare the involved variables. If you want to write a module that's instantiated in your test bench, you should know which variables are in- and outputs. And it doesn't make sense to initialize input variables..

 

[ads-ee]

Using # delays to understand the scheduling is IMO a bad idea.

The RHS of non-blocking assignments <= will all be evaluate when the always block is triggered (on the pos edge of clk). Once all the RHS have been evaluated the assignment to the LHS will occur.

I never use # delay in any code that I synthesize nor do I use it with non-blocking assignments (though it can be used in some cases).

Here is an example of your code with the correct structure around it to simulate.

---

Code Verilog - [expand]
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`timescale 1ns/1ps
module test;
 
  reg       clk = 0;
  initial begin
    // 20 ns clock period (timescale is set to 1ns)
    forever #10 clk = ~clk;
  end
 
  reg [7:0] a = 3;
  reg [7:0] b = 2;
  reg [7:0] c = 1;
  reg [7:0] d;
 
  always @(posedge clk) begin
    b <= a + a;
    # 5  c <= b + a;
    # 2  d <= c  + a;
  end
 
  initial begin
    // don't make run on statements on one line....
    // begin a = 3; b = 2; c = 1;
    // this is bad coding style IMO, make it harder to read
    // at a glance.
    //
    // assign a at time 0 same as intial values in declaration above.
    #1 a = 3;
    repeat (4) @(posedge clk);
    // change a to something else after 4 clocks
    #1 a = 5;
  end
 
  initial
    $monitor ("%t - a = %d, b = %d, c = %d, d = %d", $time, a, b, c, d);
 
 
  // without delays
  reg [7:0] e = 3;
  reg [7:0] f = 2;
  reg [7:0] g = 1;
  reg [7:0] h;
 
  always @(posedge clk) begin
    f <= e + e;
    g <= f + e;
    h <= g + e;
  end
 
  initial begin
    e = 3;
    repeat (4) @(posedge clk);
    e = 5;
  end
 
  initial
    $monitor ("%t - e = %d, f = %d, g = %d, h = %d", $time, e, f, g, h);
 
endmodule

---

Here is an output of the two different sets of assignments, notice the first set a-d is wrong (due to the # delays, which you should not be using in the blocking assignments). The second set e-h correctly shows the pipelined operation of the flip-flops.\

 

[dave_59]

Inter assignment delays can be used to model propagation delays. But an inter assignment delay of goes in the middle of of an non-blocking assignment. The OP has added a blocking delay to a procedural statement, which happens to be a non-blocking assignment. The correct, synthesizable syntax would be

always @(posedge clk) begin
    b <= a + a;
    c <= #5 b + a;
    d <= #2 c + a;
end

 

[ThisIsNotSam]

Inter assignment delays can be used to model propagation delays. But an inter assignment delay of goes in the middle of of an non-blocking assignment. The OP has added a blocking delay to a procedural statement, which happens to be a non-blocking assignment. The correct, synthesizable syntax would be

always @(posedge clk) begin
    b <= a + a;
    c <= #5 b + a;
    d <= #2 c + a;
end

I believe the OP had no idea there was an actual use for the delays as you mentioned -- he was just coding something awful to try to understand the scheduling of events. Don't ask me why.

Now, you said this was synthesisable. It is not. The compiler will ignore it, although synthesis will not fail. But I wouldn't call it synthesisable.

 

[dipin]

Hi,

How one will write the port declarations,

https://www.asic-world.com/verilog/syntax2.html
at least you will get little bit idea....refer above

i tried in various way but it shows error,
[/CODE]

post your FULL CODE including test bench and if possible error also

regards

 

[ads-ee]

Inter assignment delays can be used to model propagation delays. But an inter assignment delay of goes in the middle of of an non-blocking assignment. The OP has added a blocking delay to a procedural statement, which happens to be a non-blocking assignment. The correct, synthesizable syntax would be

always @(posedge clk) begin
    b <= a + a;
    c <= #5 b + a;
    d <= #2 c + a;
end

I'd considered pointing this out, but I feel that using # delays in your code is a crutch for those that don't understand Verilog scheduling and can't understand why the clock doesn't detect the leading edge of a transition when it changes on a clock edge, so they need to move all the transitions away from the clock edges to understand their simulation waveforms.