Noise during simulate

[Max++]

Please see in attach files.
I get this image from quartus software in Multiplex VHDL code simulation.
My question about the noise that happen in simulate graph.

What does it mean ?
and
How to do if I don't want this happen?

 

[Hippy Tesla]

Well, it could be an outter distorsion...

 

[haneet]

max,
frm wht i can see in the waveform window i think it is glitch.

 

[cydi]

It is a glitch happening because of the timing mismatch in your 'sel' logic .. thats my guess.. Look out for the settling time