[No title]

[mepriyasingh]

As an STA Engineer do we understand the design. is it required to do STA signoff ?

As an STA Engineer do we understand the design. is it required to do STA signoff, if yes then how much amount of design we want to know?

 

[D.A.(Tony)Stewart]

Re: As an STA Engineer do we understand the design. is it required to do STA signoff

You want to verify quality with experience in process and test methods. Understanding the design requirements or specifications and what are the boundaries to failure are key to identifying quality issues.

You don't have to know how to design, but rather how to find design / process related weaknesses for deviation and failure by comparison with requirements. (specs)

Deviation is measure by Cpk >>1 and failure can be measured by HALT or testing to failure with any environmental stress which can be many simultaneously including accelerated aging.

Design knowledge comes with experience to compare best practices , failure analysis and competitor comparisons.

 

[mepriyasingh]

Re: As an STA Engineer do we understand the design. is it required to do STA signoff

You want to verify quality with experience in process and test methods. Understanding the design requirements or specifications and what are the boundaries to failure are key to identifying quality issues.

You don't have to know how to design, but rather how to find design / process related weaknesses for deviation and failure by comparison with requirements. (specs)

Deviation is measure by Cpk >>1 and failure can be measured by HALT or testing to failure with any environmental stress which can be many simultaneously including accelerated aging.

Design knowledge comes with experience to compare best practices , failure analysis and competitor comparisons.

Need More clarification. do we have to understand the RTL or not. What is industry experience guy say ???

 

[D.A.(Tony)Stewart]

Re: As an STA Engineer do we understand the design. is it required to do STA signoff

That is a rather specific company and environment specific skill, not a general STA requirement. Which company are you thinking of?

 

[mepriyasingh]

Re: As an STA Engineer do we understand the design. is it required to do STA signoff

I not able to understand the meaning of CPK, i just simply want know that RTL understanding is required, if yes then how much?

 

[dpaul]

Re: As an STA Engineer do we understand the design. is it required to do STA signoff

I think it depends on what exactly is your role and the team you are working with. A STA engineer need not to understand a design at the RTL level if his/her task is only to perform STA. But if the same engineer is entrusted with the task to fix some failing timing paths in the RTL then obviously a good understanding of the design at RTL level is required.
What I have seen in complex SoC design projects is that an STA engineer for the top-level design will be in close contact with the module design engineer (RTL) and together they solve the problem. But in smaller companies or design teams, RTL engineers will perform STA.
Understanding of the functionality of each block is however necessary no matter in what stage you are.

 

[mepriyasingh]

Re: As an STA Engineer do we understand the design. is it required to do STA signoff

I think it depends on what exactly is your role and the team you are working with. A STA engineer need not to understand a design at the RTL level if his/her task is only to perform STA. But if the same engineer is entrusted with the task to fix some failing timing paths in the RTL then obviously a good understanding of the design at RTL level is required.
What I have seen in complex SoC design projects is that an STA engineer for the top-level design will be in close contact with the module design engineer (RTL) and together they solve the problem. But in smaller companies or design teams, RTL engineers will perform STA.
Understanding of the functionality of each block is however necessary no matter in what stage you are.

Thanks
this information is helpful for me..

Also is this aspect applicable for synthesis guy also. he can do synthesis without understanding of RTL

Thanks a lot in Advance.

 

[jt_eaton]

Re: As an STA Engineer do we understand the design. is it required to do STA signoff

As an STA Engineer do we understand the design. is it required to do STA signoff, if yes then how much amount of design we want to know?

You do not need to know anything about a design to do STA. Simply check that all paths meet single cycle timing requirements. If they don't and you can't relax your clock spec then you will have to learn a lot about the design so that you do not waste routing resources on false paths.

John Eaton

 

[ads-ee]

Re: As an STA Engineer do we understand the design. is it required to do STA signoff

You do not need to know anything about a design to do STA. Simply check that all paths meet single cycle timing requirements. If they don't and you can't relax your clock spec then you will have to learn a lot about the design so that you do not waste routing resources on false paths.

John Eaton

I wouldn't say routing resources here.

The RTl designer should tell the STA engineer which if any paths are multi-cycle or false, so that the STA engineer can write the correct constraints to account for paths that are not single cycle.

I would suggest unless you plan on making a career out of working exclusively on huge design teams where you are only an STA engineer (e.g. writing timing constraints, running STA, reporting timing violations) and don't do anything besides report failing paths, that you get a working familiarity with RTL code (both VHDL and Verilog). Having knowledge of STA and RTL will make you more valuable to any ASIC team you are on.