Hi
I am design one NMOS LDO with current limit function.The dropout of NMOS is 200mV.The supply is set 5.2V,the out is 5V. How can i sense the output current of ldo.
Thanks !
I think you have too much gain in the current control loop, and if the speed of the control loop is comparable with the settling speed of the main LDO feedback system, than it can cause unstability or ringing. What do you mean on that your control accuracy is poor? How much accuracy you need? In percentage. And how much is the target current limit?
You might use the metal run from pass FET source to
pad(s) as your sense resistor.
It will be difficult or impossible to get a good current mirror
fidelity with so little headroom, and your 5.2V in, 5.0V out
setup really would prefer a PMOS pass device (unless you
have an AUX supply that is well higher than VIN, for pass
FET gate overdrive range.
A NMOS current mirror that pulls on a VIN-referred burden
resistor for some up-front gain, and a subsequent active
gain / compare function, could give you a "good enough"
current limit. This depends on expectations and who gets
to set them. Does it have to be fast, have to be stable,
have to do something more complex like foldback current
profile rather than plateau, etc.
Hi
If you design from IC solution, I suggest you use complete solution as LTC (ADI) with Surge-stopper, other supplier call it is e-fuse.
It is clear that almost LDO in the market claim that it have current limit or short circuit function. But, in fact, when issue happen, LDO still spoiled. So, that protect function is no meaning.
We come back your purpose why you need current sense for LDO ?
With my experiment, it will use for 02 cases: monitor energy & protection.
If you use for monitor, you can use some specific IC, so it is more accuracy and reduce developing time. -> Used Instrument amplifier, like INA193 (for cheap), or LTC6115.
If you use for protection, you should separate the function. As the #9 said, it is un-wanted case like ringing, ad more noise to output. That mean makes LDO operate malfunction.
The most purpose of LDO is keep constant output voltage and reject noise from input power.
The proposal is Protector stand in front of which need protection. Input -> Surge stopper -> LDO/Switching -> Load.
Protector need separate from main operating object to warranty the reliability of system. Monitor system vs actuator system is independent.
You can take a look at surge stopper LT4356, it will help you multiple protect function:
limit inrush current, over/under voltage, setting time of over current (capacitor load), over voltage, reverse input voltage. And it use N-fet for lower Rdson, cost, popular, ...
My friend use LT4356, LT4380 for motor driver protect, RF power amplifier (PA) and feedback it is helpful and avoid spoiling expensive component.
So, given that this is an internal application, who is making
the current sense a requirement, and what are the required
attributes?
If the output is not exposed, or only exposed to a local
decoupling pin and no external load that could go shorted,
what is then the value of current limit? Presumably if the
on-chip LDO is presented a shorted load, it's because
there's an on-chip short (so already hosed)?
Are you building a LDO which can survive a "dead client"?
If so, what's the value proposition?
I think you could try these things:
a, add calibration to balance the error of the current mirror. It is reliable, many ways you can implement it, some example:
- analog: potentiometer instead of R
- digital: add a DAC circuit to generate 600mV comparator reference voltage, possibly low resolution is enough to reach a 1-5% percent error. Search for R-string DAC, it is small.
b, instead of the bottom comparator use an OTA with a "huge" capacitor on its output. It will slow down the current control loop.
c, to reduce the current control loop gain add source degeneration to the bottom transistor's source. A resistor or a current source maybe.
Sounds like a cryptic description of instable current control loop. That's expectable, you want to analyze loop phase margin and provide approriate frequency compensation. Hint: loop stability depends on the load impedance.During the simulation, the current control loop gain is so high to influnence main loop output. Reduce the current loop gain should be done.
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