NMOS as output buffer and its buffer capacitance

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chlee

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I am using NMOS as output buffer for my amplifier design.
Is the load resistor parallel with the NMOS buffer capacitance in small signal model?
What parameters involved in calculating the buffer capacitance?(Not include parameters which usually ignored)

Sorry for bad english. Urgent help plz...
 

all the capacitances in respect to this buffer node such as Csd, Csg, Csb, and maybe pad capacitance, inculding pin model.
i think you can simply treat it in parallel with Rload in small signal model.
 

Then what exactly is the relationship between the buffer capacitance and those 3 capacitances?
 

buffer capacitance (load capacitance) and those 3 capacitances (parasitic caps) are in parallel, too
 

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