Because of Id, Vout sits at some large-signal DC bias voltage, which is then used to bias the gate of the NFET. This is necessary since the AC coupling at the gate of the NFET will remove DC components and the NFET wouldn't be working properly unless biased at some reasonable VGS (and VDS).
The gate voltage increases (as the gate charges) through the resistor, until equilibrium is reached at some biasing point where ID1 = Id. Of course, this assumes that such a condition is possible with transistors in saturation - if not, you'll be in triode or cut-off.