# Newbie Question (regarding simulation of BUFGCE module)

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##### Newbie level 4
Hi,

I am trying to implement the clock gating technique using the global clock buffers (Virtex 5 FPGA). For a start i made a small test project just to get familiar with the funtionality of the BUFGCE, which is required to be instantiated in the code. I wrote this test module

Code:
module bufg_test(clk,ce,op);

input clk,ce;
output op;

BUFGCE BUFGCE_inst (
.O(op), // Clock buffer output
.CE(ce), // Clock enable input
.I(clk) // Clock buffer input
);

endmodule

and it's test bench

Code:
module tb_bufg_test();

reg clk;
reg ce;
wire op;
bufg_test uut(.clk(clk),.ce(ce),.op(op));

initial begin

clk = 0;
ce = 0;
//wait 100 ns for global reset to finish
#100

ce = 1;
#200 ce = 0;

#400;
\$stop;
end

always #20 clk = ~clk;

endmodule

Now the problem is that the output of the BUFGCE is not gated clock. It is exactly the copy of the input clock. I am attaching the wave window.

I am simulating it from ModelSim 6.3 (using libraries (which i compiled first) from Xilinx 10.1webpack)

Any ideas what am i doing wrong here?

#### sajal1975

##### Full Member level 2
what is ur exact prolem clearify

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