I'm trying to generate a 193.16 Mhz clock using PLL for a particular VGA resolution (1920x1200@60Hz). I understand that this can be generated from a 50Mhz oscillator (that my board happens to have) using the following multiplier/divisor: 4829/1250. My version of Quartus (12.0 .. need old version for Cyclone 2) complains that this freq is achievable. I saw some docs that suggest that the multiplier and divisor can indeed not exceed 4096. Any thoughts on how to move forward? I'm a newbie doing this as a hobby so pls be gentle.
I realized that one solution is to have two PLL blocks (I tried one that goes from 50 to 40Mhz) and the other goes to my target frequency. Quartus is giving me some pains though ... it doesn't like that the input of the second PLL is coming directly from the first PLL. Hmm...
PLL capabilities of Cyclone II are in fact limited compared to newer types, one restriction is that PLLs can only be clocked by it's assigned dedicated clock input.
But VGA monitors have typically some tolerance in frequency, you might try the nearest achievable frequency instead.
PLL capabilities of Cyclone II are in fact limited compared to newer types, one restriction is that PLLs can only be clocked by it's assigned dedicated clock input.
But VGA monitors have typically some tolerance in frequency, you might try the nearest achievable frequency instead.