micktosin
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Hello there, I programmed a code to divide my FPGA clock to my required frequency and then invert into two square wave, however I keep getting an error with the testbench stating "the module pulsegentb(file name) is instantiating itself".
And also with the file reports stating "the instantiation depth of pulsegatetb/notgate/notgate....is 51. This might indicate a recursive instantiation, increasing limit to 75".
Below is the code of the square wave generator and the test bench please can someone help me as to why I can't run the testbench?
Test Bench
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Square wave generator
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And also with the file reports stating "the instantiation depth of pulsegatetb/notgate/notgate....is 51. This might indicate a recursive instantiation, increasing limit to 75".
Below is the code of the square wave generator and the test bench please can someone help me as to why I can't run the testbench?
Test Bench
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Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module pulsegentb(); wire igbtclk1, igbtclk2; reg clock, reset; always begin #1 clock =!clock; end initial begin clock = 0; reset = 0; #10 $finish; end pulsegentb notgate(clock, igbtclock1, igbtclock2); endmodule
Square wave generator
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Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 module igbt_clock_gen (clock,reset,igbtclock1,igbtclock2); input clock,reset; output reg igbtclock1, igbtclock2; wire temp1; freq_div f1 (clock,reset,temp1); clock_multiplier c1 (temp1, igbtclock1,igbtclock2); endmodule module freq_div(clock,rst,clock_out); input clock,rst; output reg clock_out; reg [15:0] counter; always @(posedge clock or negedge rst) begin if(!rst) begin counter<=16'd0; clock_out <= 1'b0; end else if(counter==16'd6667) begin counter <= 16'd0; clock_out <= ~clock_out; end else begin counter<=counter+1; end end endmodule module clock_multiplier (clock, clock1, clock2); input clock; output clock1, clock2; assign clock1 = clock; assign clock2 = ~clock1; endmodule
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