New to VHDL (please help)

[Hammer111]

xst:1426

Hi
I'm new to VHDL coding and I need a little help.
I'm trying to make one traffic light for cars and other for pedestrian.
I made this code wich works great with simulator but when I tried to put it on chip I got this error:
ERROR:Xst:825 - "C:/sustav/test/test1.vhd" line 49: Wait statement in a procedure is not accepted.
I USED FPGA FROM MY UNIVERSITY(50 MHz kvartz) so I had to count 50000000 low to high transitions to get 1 second.

here's the code:

entity test1 is
Port ( clock : in STD_LOGIC;
key : in STD_LOGIC;
yellow : out STD_LOGIC :='0';
green : out STD_LOGIC :='1';
red : out STD_LOGIC :='0';
pred : out STD_LOGIC :='1';
pgreen : out STD_LOGIC :='0');
end test1;

architecture Behavioral of test1 is
signal sec : integer range 0 to 50 :=0;
signal nsec : integer range 0 to 50 :=0;
begin
process
begin
wait until key='1';
for j in 1 to 38 loop
for i in 1 to 50000000 loop
wait until clock='1';
nsec<=nsec+1;
end loop;
sec<=sec+1;
nsec<=0;
if ((sec<=2) or (sec>=34 and sec<=36)) then
yellow<='1';
else
yellow<='0';
end if;

if (sec>2 and sec<=36) then
red<='1';
else
red<='0';
end if;

if (sec>2 and sec<=36) then
red<='1';
else
red<='0';
end if;

if (sec>36) then
green<='1';
else
green<='0';
end if;
if (sec>5 and sec<=30) then
pgreen<='1';
pred<='0';
else
pgreen<='0';
pred<='1';
end if;
end loop;
end process;
end Behavioral;

please if someone can tell me what's wrong with it? I'm working with Xilinx ISE 8.1i
I was trying to find what's wrong for over a few days(I'm so frustrated)
I MUST SAY SIMULATOR WORKS PERFECTLY

 

[BGA]

wait statement in a procedure is not accepted

It isn't vhdl for hw.

 

[Hammer111]

xst:1426

what do you mean by it isn't vhdl for hw?

 

[aomeen]

warning:xst:1426

Well...

In VHDL work, it's not enough that the code simulates perfectky, you must check if the code is "Synthizable", meaning that f it can be put on an FPGA or converted into ASIC, many synthsis tool does this...Leonardo and most recently precision are examples

Now think, how would the FPGA waits until you press 1 ?? the way you wrote it suggest pulling, to loop and check, this is good if a microprocessor well carry the job, but there are no processor !!!

Try use if instead of wait, "if the button goes one then do ..."

Hope it helps..

 

[tkbits]

new to vhdl

It's code for a computer simulation, not for an FPGA.

First, let's pull the inner loop out and put it in a new process.

process
begin
  for j in 1 to 50000000 loop
    wait until clock = '1'
    nsec <= nsec + 1
  end loop;
end process;

We don't want to use "code location" to indicate that we are finished counting. An FPGA does not have a "program counter". We want an explicit signal.

one_second_mark <= nsec = 50000000;

process
begin
  for j in 1 to 50000000 loop
    wait until clock = '1'
    nsec <= nsec + 1
  end loop;
end process;

We also don't want to indicate the restart and counting of the counter with "code location". We want to update (count and reset) the counter under specific conditions.

one_second_mark <= nsec = 50000000;

process (clock)
begin
  if rising_edge(clock) then
    if nsec = 50000000 then
      -- if nsec was 50M before clock,
      --   set to 1 after clock.
      nsec <= 1;
    else
      nsec <= nsec + 1
    end if;
  end if;
end process;

This is probably synthesizable. Basically, what I've done is replace sequential loop logic with parallel update logic.

In my own coding style, I use std_logic_vector and start counters at 0 instead of 1. You will need to do something similar to the "for i" loop.

 

[Hammer111]

warning:xst:1988

GREAT IT WORKS
But that counter goes to ∞, I want it to start counting after key is pressed and to stop after 37 seconds

entity count1 is
    Port ( clock : in  STD_LOGIC;
			  key : in STD_LOGIC;
			  yellow : out STD_LOGIC :='0';
			  green : out STD_LOGIC :='1';
			  red : out STD_LOGIC :='0';
			  pred : out STD_LOGIC :='1';
			  pgreen : out STD_LOGIC :='0');
end count1;

architecture Behavioral of count1 is
signal sec : integer range 0 to 50 :=0;
signal nsec : integer range 0 to 50000000 :=1;
begin
process (clock)
begin
  if rising_edge(clock) then
    if nsec = 5 then   - I put 5 to have easier code suitable for test( should be 50M)
       nsec <= 1;
       sec <= sec+1;
    else
      nsec <= nsec + 1;
    end if;
  end if;
end process; 
end Behavioral;

After clicking on Synthetize I get many warnings:
WARNING:Xst:1291 - FF/Latch <nsec_0> is unconnected in block <count1>
for each nsec_0,nsec_1 etc
Is it a problem?

THANK YOU EVERYONE FOR HELPING ME AND SORRY FOR STUPID QUESTIONS

 

[meowtronics]

vhdl wait seconds

When coding in VHDL or verilog, think about hardware. You are describing the behaviour of hardware. Think about what signals are doing, don't think about how loop is executed.

When you catch this philosophy, you will master FPGA development.

At the beginning it may look the same, however, more VHDL stuff you do more you'll be aware that VHDL is not a "software" development language but hardware.

 

[tkbits]

hinder the constant cleaning in the block vhdl

GREAT IT WORKS
But that counter goes to ∞, I want it to start counting after key is pressed and to stop after 37 seconds

You will need to add the extra logic to do that.

You can add an extra "enable" layer. As coded below, when enable_counter is '0', the counter will not count or reset.

-- need to fill in the condition

enable_counter <= "condition for active counter";

process (clock)
begin
  if rising_edge(clock) then
    if enable_counter then
      if nsec = 5 then   -- I put 5 to have easier code suitable for test( should be 50M)
         nsec <= 1;
         sec <= sec+1;
      else
        nsec <= nsec + 1;
      end if;
    end if;
  end if;
end process;

After clicking on Synthetize I get many warnings:
WARNING:Xst:1291 - FF/Latch <nsec_0> is unconnected in block <count1>
for each nsec_0,nsec_1 etc
Is it a problem?

The two processes are supposed to be in the same entity/architecture. Signals in different entities are always treated as different signals, even if they have the same names.

 

[Hammer111]

if rising_edge gate level sim

Thanks for replys. I managed to get "Circuit design with VHDL" of V.A. Pedroni. I'll go through all examples. And I solved traffic light. Ony I have 3 warnings:

entity count1 is
    Port ( clock : in  STD_LOGIC;
			  key : in STD_LOGIC;
			  yellow : out STD_LOGIC :='0';
			  green : out STD_LOGIC :='1';
			  red : out STD_LOGIC :='0';
			  pred : out STD_LOGIC :='1';
			  pgreen : out STD_LOGIC :='0');
end count1;

architecture Behavioral of count1 is
signal sec : integer range 0 to 50 :=0;
signal nsec : integer range 1 to 50000000 :=1;
signal x : std_logic :='0';
signal y : std_logic :='0';
begin
process (clock,key,x,y)
begin
	if rising_edge(key) then
		y<='1';
	end if;
	if ((key='0' and x='1') or y='0') then
		nsec<=1;
		sec<=0;
	else
		if rising_edge(clock) then
			if nsec = 50000000 then
				nsec <= 1;
				sec <= sec+1;
			else
				nsec <= nsec + 1;
			end if;
			if sec>=38 then
				x<='1';
			end if;
			if sec<38 then
				x<='0';
			end if;
					if ((sec<=2) or (sec>=34 and sec<=36)) then
						yellow<='1';
					else
						yellow<='0';
					end if;
					
					if (sec>2 and sec<=36) then
						red<='1';
					else
						red<='0';
					end if;
					
					
					if (sec>36) then
						green<='1';
					else
						green<='0';
					end if;
					if (sec>5 and sec<=30) then
						pgreen<='1';
						pred<='0';
					else
						pgreen<='0';
						pred<='1';
					end if;
		 end if;
	end if;
end process; 
end Behavioral;

WARNING:Xst:1426 - The value init of the FF/Latch y hinder the constant cleaning in the block count1.

WARNING:Xst:1988 - Unit <count1>: instances <Mcompar__n0018>, <Mcompar__n0025> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_7> are dual, second instance is removed

WARNING:Xst:1988 - Unit <count1>: instances <Mcompar__n0023>, <Mcompar__n0026> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_8> are dual, second instance is removed

Should warnings be a problem putting code to FPGA?

 

[tkbits]

wait statement process dont want to use vhdl

Warnings will not prevent the creation of the load file. You will still be able to test your design on real hardware.

But they do point out potential problems.

The last two warnings tell you there was a redundancy, and it was optimized.

The first warning points to oddities of the signal "y". As posted, y is set to '1' once, and is never cleared back to '0'.

 

[Hammer111]

traffic light controller in pedroni vhdl

Thanks for help . You helped me a lot.

 

[dcreddy1980]

Hi,

u would face a problem if u simulate with the gate level netlist...since u have used initialization for some of the signals which is ok for RTL simulation but the synthesis tool ignores initialization os signals and u may see different results in the gate level netlist.....try to check u r gate level simulation

Regards,
dcreddy

 

[nav_vlsi]

also before writing VHDL code , get a good idea of various statements which can be synthesised and which cannot be synthesised. dont try to implement the algorithm like a software code, analyse the algo , draw a rough schematic . identify how this algo will be converted to hardware . do your paper work correctly before start coding.

 

[benzwishc]

when u use hdl to describe ur circuit ,keep logic gates and interconnect idea in mind, it is not the software, it has to meet the rules on hardware

 

[rs_408]

hi evrey one;

i need some Vhdl Files about 7 Segment counter(4 digit). and Moris Mano Cpu's Design in vhdl. also any other kind of ALU's are wellcom.

tnx to all