DefconNowhere
Junior Member level 1
Hi all,
In Cadence Virtuoso Layout-L tool, I am trying to extract my chip power grid from the top layout and simulate it. I open the top layout and use Connectivity->Nets->Mark to trace connectivity and highlight Supply and Ground nets in the top layout. I ensure vias are included for saving as well as limit connectivity tracing down to metal 5 only. Once highlight is complete, I use Connectivity->Nets->Save All MarkNets to save all highlighted nets in a new layout. That is basically my power grid in the new layout.
I open this new layout, all is fine except I see pin labels are missing. It looks like they are removed somehow as a result of saving nets operation or just not highlighted in the first place.
Is there a way to include pin labels in the Saved Net Connectivity results?
Tnx!
DefconNowhere
In Cadence Virtuoso Layout-L tool, I am trying to extract my chip power grid from the top layout and simulate it. I open the top layout and use Connectivity->Nets->Mark to trace connectivity and highlight Supply and Ground nets in the top layout. I ensure vias are included for saving as well as limit connectivity tracing down to metal 5 only. Once highlight is complete, I use Connectivity->Nets->Save All MarkNets to save all highlighted nets in a new layout. That is basically my power grid in the new layout.
I open this new layout, all is fine except I see pin labels are missing. It looks like they are removed somehow as a result of saving nets operation or just not highlighted in the first place.
Is there a way to include pin labels in the Saved Net Connectivity results?
Tnx!
DefconNowhere