[PIC] Nested Delay Loop Theory

[jamesr]

Hi,

I have looked around at Delay examples and many of the forums suggest using a nested loop to create large delays. Most of the forums point to a Delay generator tool which creates the code for you based on the clock freq and delay. This is great for implementation but for those of us learning how that works it's not as these generators seldom explain the theory. I am attempting to understand it myself so please correct my workings out where necessary so I can get an idea of where I may be going wrong.

I used the generator to create a 1 sec delay for a 20mhz clock and this is what I got;

Now my question is around how this gets to 4999993 cycles. Based on this being for a PIC device, I understand that a 20Mhz clock / 4 gives 5Million cycles per sec, so the figure below is near enough.

Each loop takes 7 cycles (from my working out).

The first counter will give;

(44 * 7) -5 = 303 - The minus 5 is for the incomplete loop as only 2 cycles have occurred on the last loop when cnt1=0

Second counter gives;

(255 * 231 * 7) -4 = 412,335 - The minus 3 is for the incomplete loop as 4 have executed on the last loop when cnt2=0

Third Counter:

Now this is where I get lost, essentially the outer loop counts 11 times, but it's not as simple as 11 * 412,335 as this doesn't stack up, and besides the counters (cnt1/cnt2) will still count backwards from 255 through to 0 again, so this means for each of the 11 loops the value is;

(255 *7-5) * (255*7 -3) * 11, but that gives 34,891,560 which clearly isn't right.

Can anyone shed some light on how the theory of calculating this works?

Thanks

dlay_loop
			;4999993 cycles
	movlw	d'44'
	movwf	cnt1
	movlw	d'231'
	movwf	cnt2
	movlw	d'11'
	movwf	cnt3
dlay_loop_0
	decfsz	cnt1, f		
	goto	$+2			
	decfsz	cnt2, f		
	goto	$+2			
	decfsz	cnt3, f		
	goto	dlay_loop_0	

	;3 cycles,
	goto	$+1
	nop

	;4 cycles (including call)
	return

 

[jayanth.devarayanadurga]

4999993 cycles is the machine cycles not loop count.

 

[jamesr]

Yes, I understand that; I have factored into the math the "7 machine cycles" that each loop takes. Based on the data sheet for a PIC16F877A. Can you expand on what you mean in relation to my question about the calculations?

Thanks

 

[wp100]

Hi,

You are nearly there in your assumptions, but you have missed one important point.

Look at the Pic16F877a datasheet, section Instruction Set Summary, the first few pages list all the possible Instructions, in those headings you can see a section labelled Cycles, thats the number of machine cycles, Fosc/4 as you say.

Many instructions take 1 cycle, but some, like the decfsz can take 2 or more.

The best way to see this happening is to use MPlabs Simulator where you can single step thought the program loop and count the actual cycles, though don't know if you are using Mplab or MMs own software or if that has such a similar feature.

 

[bigdogguru]

Several of the Gooligum Baseline and Midrange PIC tutorials discuss in detail the design and implementation of software delay routines

Particularly the following:














BigDog

 

[jamesr]

Hi, Yes I am using MPLAB.

I had a go through the data sheet and count them up, I calculated 7 cycles for a complete loop round to the start of each cnt decfsz. I will run MPLAB stopwatch and see what figures I get at each breakpoint for the counters.

- - - Updated - - -

Thanks for these, that first PDF seems to have a very well documented loop and how the figures stack up, I will read this and see how it applies to my code. Cheers

 

[wp100]

Hi,

Will have to plead guilty as that delay is not 4 seconds,:lol: if your see the original site for creation of the code it includes three 'goto $+1' instructions at the end of the routine to produce an exact 4 seconds; I just left them out to keep the code clean looking.
**broken link removed**

Importantly, avoid using $+1 type of instructions as if you migrate your code to other pic chips like the 18F the code will fail.
Instead always use 'goto label' as I have done with that delay code