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Nested classes comes from C++, it simply a way to hide the definition of a class from the outside, if that class is only to be used by the class that contains it.
You really don't need to use it in SystemVerilog because it has the concept of packages, which is more general than just for classes.
Thanks dave_59
ya you are right.. but in Testbench.in they have shown the concept but i want the small code for the same to understand how it really works in systemverilog.
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