Hi all!
I am a student studying digital design in the university.
I have a question about Synopsys IC Compiler commands which can help reduce negative setup slack in the clock gate path. I know that this situation because of late arrival of launch clock (i.e. clock skew) in comparison with capture (for clock gate) - launch clock delay is more than capture clock delays.
So, how I can solve this problem? May be there is some commands for ICC compiler?
late arrival vs early arrival is usually taken care at the clock tree step, and it should be transparent whether any of the individual clock signals are gated or not.
the fix is to get timing to pass. take a look at your clock tree targets and at your overall clock period.
Thank you for your answer!
Do you mean that during CTS all clocks will be treated as clocks without clock gated cells, and ICC optimizes skew like there is no clock gated cells inside the clock tree?
In my timing report after CTS I can see that clock network delay for launch is 0.43 and clock network delay for capture is 0.16. But report_clock_tree gives me clock skew 0.13 (for the same scenario). Why there is difference?
Thank you for your answer!
Do you mean that during CTS all clocks will be treated as clocks without clock gated cells, and ICC optimizes skew like there is no clock gated cells inside the clock tree?
In my timing report after CTS I can see that clock network delay for launch is 0.43 and clock network delay for capture is 0.16. But report_clock_tree gives me clock skew 0.13 (for the same scenario). Why there is difference?
you need to do some reading on clock trees. from CTS point of view, doesn't matter if the endpoint is a flop, a clock gating cell, a macro. it will balance and skew all of them as needed.
I don't use ICC so I can't tell you what the report_clock_tree command does differently.