They cannot overlap.
The series capacitors are an easy way to create this train of signals.
It is not called a delay, instead it is a simple timer.
1) In the upper schematic there is an RC delay on the left side that you did not see, and on the right side there are two fast (no delay) latching circuits that you circled and wrongly labeled "RC delay".
Again you are showing us that .....So it's an RC passive timer? not an RC network delay?
And again you are showing us that .....But there is an RC network, what does that RC network do? its a waveshaping RC network?
A network delay might be only 50ns
This timer is about 3 seconds which is 60 million times longer.
It is NOT an slow RC, instead it is a fast CR which is the opposite.
When the output of the 4093 suddenly goes high then the capacitor passes the leading edge of the pulse to the resistor. The resistor discharges the capacitor in about (0.047uF x 4.75k ohms)= 223us.
the capacitor passes the leading edge of the pulse to the resistor.
The Schmitt trigger NAND gate and the Schmitt trigger inverters are wave-shaping circuits that convert a slow ramp into a fast pulse.
A Schmitt trigger converts a slow ramp into a sudden very fast edge. The circuit with the Schmitt trigger NAND and Schmitt trigger inverters create logic pulses that have fast edges.
I do not understand what you said here.Yea but the way you say it , it that the Pulse width of these pulses are very short and the timing got faster, which doubled in time from using a Gate and schmitt trigger
ABSOLUTELY NOT!!!!!a Gate and schmitt trigger outputs 50% duty cycle square waveform
A gate output has the duty cycle determined by its input logic.
Schmitt trigger inputs then it will produce very fast edges even if they are slow ramps.
Of course not. The logic determines the output duty cycle.What duty cycle is a TTL or Cmos gate output? Is it the same duty cycle as the input? or what ratio is the duty cycle ?
Positive feedback makes it have "snap action".What is inside a schmitt trigger internally that makes the Edges Fast and Sharp? what component does this?
A Schmitt trigger is a circuit design, it is not a component. Some gates have it and some gates do not have it.Because Logic TTL or Cmos Gates don't have this component internally to create fast and sharp edges, any reason why?
Of course not. The logic determines the output duty cycle.
.Positive feedback makes it have "snap action"
If you ever learn what a Schmitt trigger does (I explained it many times) then you will know why it is used and why it is needed sometimes.
So the logics input determines the output duty cycle, which is the SAME as the input or how much of a time ratio of the input does the outputs duty cycle? If the logic input is 30% duty cycle, the output is 30% duty cycle?
Look it up in Google.Oh ok so a schmitt trigger has internal positive feedback circuits to make it have a sharp , fast edges?
Correct, but they have no effect on the duty cycle so the outputs are not always a 50% squarewave.The only reason they use schmitt triggers is to sharpen the edges and square off , clean up the waveform from noise and irregular shapes , rounded, etc.
It just to clean up and square off
Correct, but they have no effect on the duty cycle so the outputs are not always a 50% squarewave.
The logic on ALL the inputs determines the output duty cycle.
Bad English again. You should ask, "So what is the duty cycle then?" Look up the words THAN and THEN in a dictionary.So what is the duty cycle than?
You do not understand digital logic, timing, duty cycle, ratio or percentage so STOP ASKING ABOUT THEM!The Timing of the Logic Inputs will be the SAME time on the output or will it be different than the inputs time and duty cycle? how much of the difference is the timing and duty cycle is based on what ratio or percentage of the timing and duty cycle of the input signals?
You must analyse ALL the inputs to see what the output duty cycle is supposed to be.
The data sheet of almost every logic device has a truth table in it. The table lists what should come out for a given set of input conditions.
What are you on about?? That is absolute nonsense and what exactly is a digital ramp voltage supposed to be?? Digital logic only has two input states so how can you say it is a 'ramp'.You can apply a slow ramp input voltage and a Gate will output a short duty cycle pulse
ONLY a Schmitt trigger input converts a slow ramp into a fast edge. An ordinary gate without Schmitt trigger inputs will probably just oscillate or amplify noise.You can apply a slow ramp input voltage and a Gate will output a short duty cycle pulse
Truth tables tell you if the output will be high or low with certain inputs.The Truth Tables or Datasheets don't tell you about the duty cycles on the output from a given set of input conditions
A gate does not create a "short duty cycle pulse" because a series coupling capacitor feeding a resistor to ground helps a Schmitt trigger input DOO DAT.
ONLY a Schmitt trigger input converts a slow ramp into a fast edge.
You do not understand that the duty-cycle is defined by the pulse width. The pulse width is created by input pulses timing.
Absolutely WRONG!My Manager said that you can force a logic High to a Logic Low by grounding it , only on logic inverters and schmitt triggers because they don't have output transistors on the output stages internally , is this true?
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