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[SOLVED] Negative Logic gates, when are they used and why?

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danny davis

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They cannot overlap.
What u mean by the pulses can't overlap? explain more please

The series capacitors are an easy way to create this train of signals.
What do you mean how the series cap creates this train of signals? what kind of signals? are they spikes? train of spikes?

It is not called a delay, instead it is a simple timer.
So it's an RC passive timer? not an RC network delay?

1) In the upper schematic there is an RC delay on the left side that you did not see, and on the right side there are two fast (no delay) latching circuits that you circled and wrongly labeled "RC delay".
But there is an RC network, what does that RC network do? its a waveshaping RC network?
 

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So it's an RC passive timer? not an RC network delay?
Again you are showing us that .....
A network delay might be only 50ns. This timer is about 3 seconds which is 60 million times longer.

But there is an RC network, what does that RC network do? its a waveshaping RC network?
And again you are showing us that .....
It is NOT an slow RC, instead it is a fast CR which is the opposite.
When the output of the 4093 suddenly goes high then the capacitor passes the leading edge of the pulse to the resistor. The resistor discharges the capacitor in about (0.047uF x 4.75k ohms)= 223us. The input of the inverter suddenly goes positive for 223us then it goes low and the output of the inverter is a negative pulse which is fed back to an input on the 4093. One of the 4093 circuits is driven by inverter U6D from the 3 seconds timer. The outputs of these 223us pulse generators occur 3 seconds apart and feed the Mickey Mouse AND gate made with the two diodes that feed the opamp on the right side.
If you ever learn electronics then you will see these things immediately like we do.

The Schmitt trigger NAND gate and the Schmitt trigger inverters are wave-shaping circuits that convert a slow ramp into a fast pulse.
 

danny davis

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A network delay might be only 50ns
A network delay, you mean the stray RC from PC board traces? or the Delays from input and outputs of Logic IC chips?

This timer is about 3 seconds which is 60 million times longer.
How do you know it's a timer? because the capacitor goes to ground? or the capacitors value?

So if the RC networks time constant is a 1 second or more , you consider it a Passive RC timer?

It is NOT an slow RC, instead it is a fast CR which is the opposite.
When the output of the 4093 suddenly goes high then the capacitor passes the leading edge of the pulse to the resistor. The resistor discharges the capacitor in about (0.047uF x 4.75k ohms)= 223us.
So the CR network is a waveshaping network? it creates a Spike waveshape?

the capacitor passes the leading edge of the pulse to the resistor.
It passes the leading edge to the resistor , but the capacitor discharges the Top and falling edge of the pulse creating a Spike or shark fin looking waveform

The Schmitt trigger NAND gate and the Schmitt trigger inverters are wave-shaping circuits that convert a slow ramp into a fast pulse.
How can they convert a slow ramp into a fast pulse?

I through gates and schmitt triggers square and gate whatever input is has
 

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A Schmitt trigger converts a slow ramp into a sudden very fast edge. The circuit with the Schmitt trigger NAND and Schmitt trigger inverters create logic pulses that have fast edges.
 

danny davis

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A Schmitt trigger converts a slow ramp into a sudden very fast edge. The circuit with the Schmitt trigger NAND and Schmitt trigger inverters create logic pulses that have fast edges.
Yea but the way you say it , it that the Pulse width of these pulses are very short and the timing got faster, which doubled in time from using a Gate and schmitt trigger

a Gate and schmitt trigger outputs 50% duty cycle square waveform
 

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Yea but the way you say it , it that the Pulse width of these pulses are very short and the timing got faster, which doubled in time from using a Gate and schmitt trigger
I do not understand what you said here.

a Gate and schmitt trigger outputs 50% duty cycle square waveform
ABSOLUTELY NOT!!!!!
Only a binary digital divider outputs a 50% duty cycle square waveform.

A gate output has the duty cycle determined by its input logic. It can produce DC, very narrow pulses or very wide pulses at its output. It can have Schmitt trigger inputs then it will produce very fast edges even if they are slow ramps. A Schmitt trigger inverter also produces very fast edges even if they are slow ramps.
Some counter/divider ICs like the CD4017 has a Schmitt trigger clock input.
A Schmitt trigger input can produce any duty cycle.
 

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A gate output has the duty cycle determined by its input logic.
What duty cycle is a TTL or Cmos gate output? Is it the same duty cycle as the input? or what ratio is the duty cycle ?

Schmitt trigger inputs then it will produce very fast edges even if they are slow ramps.
What is inside a schmitt trigger internally that makes the Edges Fast and Sharp? what component does this?

Because Logic TTL or Cmos Gates don't have this component internally to create fast and sharp edges, any reason why?
 

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What duty cycle is a TTL or Cmos gate output? Is it the same duty cycle as the input? or what ratio is the duty cycle ?
Of course not. The logic determines the output duty cycle.

What is inside a schmitt trigger internally that makes the Edges Fast and Sharp? what component does this?
Positive feedback makes it have "snap action".
Instead of asking millions of your very simple questions about the basics of electronics, why don't you find out for yourself? Look in Google or go back to school!

Because Logic TTL or Cmos Gates don't have this component internally to create fast and sharp edges, any reason why?
A Schmitt trigger is a circuit design, it is not a component. Some gates have it and some gates do not have it.
Usually logic gates switch fast enough and do not need Schmitt triggers. If you ever learn what a Schmitt trigger does (I explained it many times) then you will know why it is used and why it is needed sometimes.
 

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Of course not. The logic determines the output duty cycle.
So the logics input determines the output duty cycle, which is the SAME as the input or how much of a time ratio of the input does the outputs duty cycle?

If the logic input is 30% duty cycle, the output is 30% duty cycle?

Positive feedback makes it have "snap action"
.

Oh ok so a schmitt trigger has internal positive feedback circuits to make it have a sharp , fast edges?

If you ever learn what a Schmitt trigger does (I explained it many times) then you will know why it is used and why it is needed sometimes.
The only reason they use schmitt triggeres is to sharpen the edges and square off , clean up the waveform from noise and irregular shapes , rounded, etc.

It just to clean up and square off
 

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So the logics input determines the output duty cycle, which is the SAME as the input or how much of a time ratio of the input does the outputs duty cycle? If the logic input is 30% duty cycle, the output is 30% duty cycle?
Of course not. Now you are showing us that you understand NOTHING about logic circuits.
Gates have more than one input. The logic on ALL the inputs determines the output duty cycle.

Oh ok so a schmitt trigger has internal positive feedback circuits to make it have a sharp , fast edges?
Look it up in Google.

The only reason they use schmitt triggers is to sharpen the edges and square off , clean up the waveform from noise and irregular shapes , rounded, etc.
It just to clean up and square off
Correct, but they have no effect on the duty cycle so the outputs are not always a 50% squarewave.
 

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Correct, but they have no effect on the duty cycle so the outputs are not always a 50% squarewave.
So what is the duty cycle than?

The logic on ALL the inputs determines the output duty cycle.
The Timing of the Logic Inputs will be the SAME time on the output or will it be different than the inputs time and duty cycle? how much of the difference is the timing and duty cycle is based on what ratio or percentage of the timing and duty cycle of the input signals?
 

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So what is the duty cycle than?
Bad English again. You should ask, "So what is the duty cycle then?" Look up the words THAN and THEN in a dictionary.

The duty cycle is determined by the logic of the inputs. Maybe one input has a DC voltage or signal that is gated on and off by another input. Maybe a third or fourth input gates the gated DC or signal on and off. You must analyse ALL the inputs to see what the output duty cycle is supposed to be.

The Timing of the Logic Inputs will be the SAME time on the output or will it be different than the inputs time and duty cycle? how much of the difference is the timing and duty cycle is based on what ratio or percentage of the timing and duty cycle of the input signals?
You do not understand digital logic, timing, duty cycle, ratio or percentage so STOP ASKING ABOUT THEM!
 

danny davis

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You must analyse ALL the inputs to see what the output duty cycle is supposed to be.
I understand that, but what I don't understand is how do you add up the time ratios of the inputs to get the output result

My 0-Scope has cursors to measure the Time Ratios , So If I measure both logic gates input time ratios this should add up to make the output duty cycle?
 

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This is basic logic. Look up what is SUPPOSED to come out of different logic gates when your inputs are applied. If something different comes out you have a faulty part or something elsewhere is preventing the output changing state. The data sheet of almost every logic device has a truth table in it. The table lists what should come out for a given set of input conditions.

Adding logic inputs makes no sense whatsoever and time ratios, whatever you think they are, are irrelevant.

If you want to test the actual logic operation of a gate, meaning looking at several inputs and the outputs at the same time, you need a logic analyser, no other tool will do it. However, I would stress that in your work and level of expertise, a logic analyser would be wasted. It is more of a development tool than for fault finding.

Brian.
 

danny davis

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The data sheet of almost every logic device has a truth table in it. The table lists what should come out for a given set of input conditions.
The Truth Tables, don't tell you what the Duty Cycle is going to be on the output from a given set of input conditions

You can apply a slow ramp input voltage and a Gate will output a short duty cycle pulse

The Truth Tables or Datasheets don't tell you about the duty cycles on the output from a given set of input conditions
 

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You are missing the point completely - The truth tables tell you what output to expect for any given input. The 'duty cycle' as you call it is entirely dependant on the state of the inputs. If you change the inputs, the output also changes so you can't say on a data sheet that the output will be any particular value without qualifying the input state at that time.

You can apply a slow ramp input voltage and a Gate will output a short duty cycle pulse
What are you on about?? That is absolute nonsense and what exactly is a digital ramp voltage supposed to be?? Digital logic only has two input states so how can you say it is a 'ramp'.

Brian.
 

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You can apply a slow ramp input voltage and a Gate will output a short duty cycle pulse
ONLY a Schmitt trigger input converts a slow ramp into a fast edge. An ordinary gate without Schmitt trigger inputs will probably just oscillate or amplify noise.
A gate does not create a "short duty cycle pulse" because a series coupling capacitor feeding a resistor to ground helps a Schmitt trigger input DOO DAT.

The Truth Tables or Datasheets don't tell you about the duty cycles on the output from a given set of input conditions
Truth tables tell you if the output will be high or low with certain inputs.

You do not understand that the duty-cycle is defined by the pulse width. The pulse width is created by input pulses timing.
 

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A gate does not create a "short duty cycle pulse" because a series coupling capacitor feeding a resistor to ground helps a Schmitt trigger input DOO DAT.
yes its the CR network that creates the short duty cycle pulse , not the schmitt trigger

ONLY a Schmitt trigger input converts a slow ramp into a fast edge.
A Gate will convert a ramp voltage into a square waveform voltage

You do not understand that the duty-cycle is defined by the pulse width. The pulse width is created by input pulses timing.
Yes I know the pulse width is created by input pulse timing

But a Gate or Schmitt trigger will not be the SAME timing and pulse width as the input, the output will be different than the input

------------------------

My Manager said that you can force a logic High to a Logic Low by grounding it , only on logic inverters and schmitt triggers because they don't have output transistors on the output stages internally , is this true?
 

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My Manager said that you can force a logic High to a Logic Low by grounding it , only on logic inverters and schmitt triggers because they don't have output transistors on the output stages internally , is this true?
Absolutely WRONG!
A logic inverter and a Schmitt trigger WILL NOT WORK if they had no transistors on their output. If you short an active high output to ground then the output might burn out. Try it and let us know but try at least 10 ICs. TTL and Cmos logic ICs are completely different so try shorting both.

An open collector output (it goes low but does not go high) can be shorted to ground and needs a pullup resistor to make it go high. A few old TTL gates had open collector outputs. No inverters have open collector outputs. Schmitt triggers are on inputs not outputs so they also do not have open collector outputs.
Most comparator ICs have open collector outputs.
 

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An Op Amp Configured as an Op amp comparator , my manager calls them differential amps, but they are not differential amps , they are Op am comparators but he calls the differential amps
 

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